drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

45

#define HOST_SESSION_MASK REG_GENMASK64(63, 60)

drivers/gpu/drm/i915/i915_reg.h

1219

#define GEN6_BDSM_MASK REG_GENMASK64(31, 20)

drivers/gpu/drm/i915/i915_reg.h

1220

#define GEN11_BDSM_MASK REG_GENMASK64(63, 20)

drivers/gpu/drm/i915/intel_mchbar_regs.h

241

#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)

drivers/gpu/drm/i915/intel_mchbar_regs.h

242

#define SSKPD_WM4_MASK_HSW REG_GENMASK64(40, 32)

drivers/gpu/drm/i915/intel_mchbar_regs.h

243

#define SSKPD_WM3_MASK_HSW REG_GENMASK64(28, 20)

drivers/gpu/drm/i915/intel_mchbar_regs.h

244

#define SSKPD_WM2_MASK_HSW REG_GENMASK64(19, 12)

drivers/gpu/drm/i915/intel_mchbar_regs.h

245

#define SSKPD_WM1_MASK_HSW REG_GENMASK64(11, 4)

drivers/gpu/drm/i915/intel_mchbar_regs.h

246

#define SSKPD_OLD_WM0_MASK_HSW REG_GENMASK64(3, 0)

drivers/gpu/drm/xe/regs/xe_pmt.h

15

#define ENERGY_PKG REG_GENMASK64(31, 0)

drivers/gpu/drm/xe/regs/xe_pmt.h

16

#define ENERGY_CARD REG_GENMASK64(63, 32)

drivers/gpu/drm/xe/regs/xe_regs.h

36

#define BDSM_MASK REG_GENMASK64(63, 20)

drivers/gpu/drm/xe/regs/xe_regs.h

41

#define WOPCM_SIZE_MASK REG_GENMASK64(9, 7)