drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

342

#define C20_PHY_TX_MISC_MASK REG_GENMASK16(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

344

#define C20_PHY_TX_DCC_CAL_RANGE_MASK REG_GENMASK16(11, 8)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

348

#define C20_PHY_TX_TERM_CTL_MASK REG_GENMASK16(15, 13)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

399

#define MPLLB_ANA_FREQ_VCO_MASK REG_GENMASK16(15, 14)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

402

#define MPLL_DIV_MULTIPLIER_MASK REG_GENMASK16(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

406

#define CAL_DAC_CODE_MASK REG_GENMASK16(14, 10)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

410

#define CP_INT_GS_MASK REG_GENMASK16(6, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

414

#define CP_PROP_GS_MASK REG_GENMASK16(13, 7)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

418

#define CP_INT_MASK REG_GENMASK16(6, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

422

#define CP_PROP_MASK REG_GENMASK16(13, 7)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

426

#define V2I_MASK REG_GENMASK16(15, 14)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

430

#define HDMI_DIV_MASK REG_GENMASK16(2, 0)