drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
110
#define IREF0RC_OFFSET_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
116
#define IREF1RC_OFFSET_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
124
#define SUS_CLK_CONFIG REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
148
#define GRC_CODE_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
150
#define GRC_CODE_FAST_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
152
#define GRC_CODE_SLOW_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
154
#define GRC_CODE_NOM_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
191
#define LANE_STAGGER_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
215
#define MARGIN_000_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
217
#define UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
247
#define DE_EMPHASIS_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
47
#define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
49
#define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
68
#define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
71
#define PORT_PLL_N_MASK REG_GENMASK(11, 8)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
74
#define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
79
#define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
81
#define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
83
#define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
86
#define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
89
#define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
93
#define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
101
#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
103
#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
109
#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
18
#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
34
#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
59
#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
61
#define DISP_POS_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
66
#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
68
#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
73
#define DISP_ADDR_MASK REG_GENMASK(31, 12)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
77
#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
79
#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
94
#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
96
#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
222
#define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
223
#define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
224
#define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
232
#define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
233
#define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
234
#define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
235
#define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
236
#define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/i9xx_wm_regs.h
246
#define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/display/icl_dsi_regs.h
101
#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
drivers/gpu/drm/i915/display/icl_dsi_regs.h
109
#define DSI_T_INIT_MASTER_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/icl_dsi_regs.h
33
#define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_audio_regs.h
13
#define G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9)
drivers/gpu/drm/i915/display/intel_audio_regs.h
14
#define G4X_ELD_ADDRESS_MASK REG_GENMASK(8, 5)
drivers/gpu/drm/i915/display/intel_audio_regs.h
26
#define IBX_ELD_BUFFER_SIZE_MASK REG_GENMASK(14, 10)
drivers/gpu/drm/i915/display/intel_audio_regs.h
27
#define IBX_ELD_ADDRESS_MASK REG_GENMASK(9, 5)
drivers/gpu/drm/i915/display/intel_audio_regs.h
60
#define AUD_CONFIG_UPPER_N_MASK REG_GENMASK(27, 20)
drivers/gpu/drm/i915/display/intel_audio_regs.h
61
#define AUD_CONFIG_LOWER_N_MASK REG_GENMASK(15, 4)
drivers/gpu/drm/i915/display/intel_audio_regs.h
66
#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_audio_regs.h
96
#define AUD_CONFIG_M_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_casf_regs.h
15
#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_casf_regs.h
17
#define FILTER_SIZE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_casf_regs.h
30
#define INDEX_VALUE_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/intel_cmtg_regs.h
12
#define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)
drivers/gpu/drm/i915/display/intel_cmtg_regs.h
14
#define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13)
drivers/gpu/drm/i915/display/intel_color_regs.h
16
#define PALETTE_RED_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_color_regs.h
17
#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_color_regs.h
18
#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
20
#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_color_regs.h
204
#define PAL_PREC_INDEX_VALUE_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
21
#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_color_regs.h
22
#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
230
#define PRE_CSC_GAMC_INDEX_VALUE_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
24
#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
drivers/gpu/drm/i915/display/intel_color_regs.h
243
#define PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
25
#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
drivers/gpu/drm/i915/display/intel_color_regs.h
26
#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/intel_color_regs.h
27
#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
drivers/gpu/drm/i915/display/intel_color_regs.h
279
#define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16)
drivers/gpu/drm/i915/display/intel_color_regs.h
28
#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
drivers/gpu/drm/i915/display/intel_color_regs.h
280
#define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
282
#define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
285
#define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16)
drivers/gpu/drm/i915/display/intel_color_regs.h
286
#define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
288
#define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
29
#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
drivers/gpu/drm/i915/display/intel_color_regs.h
30
#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/display/intel_color_regs.h
31
#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
drivers/gpu/drm/i915/display/intel_color_regs.h
32
#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
325
#define LUT_3D_BINDING_MASK REG_GENMASK(23, 22)
drivers/gpu/drm/i915/display/intel_color_regs.h
335
#define LUT_3D_INDEX_VALUE_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
341
#define LUT_3D_DATA_RED_MASK REG_GENMASK(29, 20)
drivers/gpu/drm/i915/display/intel_color_regs.h
342
#define LUT_3D_DATA_GREEN_MASK REG_GENMASK(19, 10)
drivers/gpu/drm/i915/display/intel_color_regs.h
343
#define LUT_3D_DATA_BLUE_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
54
#define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20)
drivers/gpu/drm/i915/display/intel_color_regs.h
55
#define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10)
drivers/gpu/drm/i915/display/intel_color_regs.h
56
#define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
58
#define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24)
drivers/gpu/drm/i915/display/intel_color_regs.h
59
#define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14)
drivers/gpu/drm/i915/display/intel_color_regs.h
60
#define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4)
drivers/gpu/drm/i915/display/intel_color_regs.h
62
#define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20)
drivers/gpu/drm/i915/display/intel_color_regs.h
63
#define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10)
drivers/gpu/drm/i915/display/intel_color_regs.h
64
#define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_color_regs.h
77
#define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
112
#define SWING_SEL_LOWER_MASK REG_GENMASK(13, 11)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
114
#define FRC_LATENCY_OPTIM_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
116
#define RCOMP_SCALAR_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
123
#define POST_CURSOR_1_MASK REG_GENMASK(17, 12)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
125
#define POST_CURSOR_2_MASK REG_GENMASK(11, 6)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
127
#define CURSOR_COEFF_MASK REG_GENMASK(5, 0)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
138
#define SCALING_MODE_SEL_MASK REG_GENMASK(20, 18)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
140
#define RTERM_SELECT_MASK REG_GENMASK(5, 3)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
147
#define O_LDO_REF_SEL_CRI REG_GENMASK(6, 1)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
153
#define N_SCALAR_MASK REG_GENMASK(30, 24)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
160
#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
29
#define SUS_CLOCK_CONFIG REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
32
#define PG_SEQ_DELAY_OVERRIDE_MASK REG_GENMASK(26, 25)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
34
#define PWR_DOWN_LN_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
60
#define PROCESS_INFO_MASK REG_GENMASK(28, 26)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
64
#define VOLTAGE_INFO_MASK REG_GENMASK(25, 24)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
89
#define DCC_MODE_SELECT_MASK REG_GENMASK(21, 20)
drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
92
#define LATENCY_OPTIM_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/display/intel_crt_regs.h
17
#define ADPA_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_crt_regs.h
19
#define ADPA_CRT_HOTPLUG_MONITOR_MASK REG_GENMASK(25, 24)
drivers/gpu/drm/i915/display/intel_crt_regs.h
33
#define ADPA_CRT_HOTPLUG_VOLTAGE_MASK REG_GENMASK(19, 18)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
102
#define CUR_BUF_END_MASK REG_GENMASK(27, 16)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
104
#define CUR_BUF_START_MASK REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
16
#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
18
#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
25
#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
drivers/gpu/drm/i915/display/intel_cursor_regs.h
27
#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
49
#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
52
#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
60
#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
62
#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
68
#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
83
#define CUR_WM_LINES_MASK REG_GENMASK(26, 14)
drivers/gpu/drm/i915/display/intel_cursor_regs.h
84
#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
102
#define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
107
#define XE3PLPDP_PHY_MODE_MASK REG_GENMASK(15, 12)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
114
#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
131
#define _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
133
#define _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
138
#define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
139
#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
151
#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
153
#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
176
#define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
199
#define _XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
200
#define _XE3_DDI_CLOCK_SELECT_MASK REG_GENMASK(16, 12)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
226
#define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
263
#define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
264
#define C10_CMN0_REF_CLK_MPLLB_DIV REG_FIELD_PREP(REG_GENMASK(7, 5), 1)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
276
#define C10_VDR_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
314
#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
341
#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
361
#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
368
#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
370
#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
371
#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
49
#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
54
#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
57
#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
70
#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
73
#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
1071
#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
drivers/gpu/drm/i915/display/intel_display_regs.h
1079
#define PS_BINDING_MASK REG_GENMASK(27, 25)
drivers/gpu/drm/i915/display/intel_display_regs.h
1082
#define PS_FILTER_MASK REG_GENMASK(24, 23)
drivers/gpu/drm/i915/display/intel_display_regs.h
1099
#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
drivers/gpu/drm/i915/display/intel_display_regs.h
1103
#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
drivers/gpu/drm/i915/display/intel_display_regs.h
1123
#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
drivers/gpu/drm/i915/display/intel_display_regs.h
1128
#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
1142
#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
1144
#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
1155
#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
1157
#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
1186
#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
1188
#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
1397
#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
1399
#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
1401
#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/display/intel_display_regs.h
1403
#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
1418
#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
1419
#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
drivers/gpu/drm/i915/display/intel_display_regs.h
1420
#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
1421
#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/i915/display/intel_display_regs.h
1422
#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/display/intel_display_regs.h
1423
#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/i915/display/intel_display_regs.h
1424
#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
1427
#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
drivers/gpu/drm/i915/display/intel_display_regs.h
1428
#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
1429
#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
drivers/gpu/drm/i915/display/intel_display_regs.h
1430
#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
1466
#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
1488
#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
drivers/gpu/drm/i915/display/intel_display_regs.h
1517
#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
1556
#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
drivers/gpu/drm/i915/display/intel_display_regs.h
1557
#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
drivers/gpu/drm/i915/display/intel_display_regs.h
1559
#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
drivers/gpu/drm/i915/display/intel_display_regs.h
2012
#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
drivers/gpu/drm/i915/display/intel_display_regs.h
2014
#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
drivers/gpu/drm/i915/display/intel_display_regs.h
2018
#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
drivers/gpu/drm/i915/display/intel_display_regs.h
2034
#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_display_regs.h
2039
#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
drivers/gpu/drm/i915/display/intel_display_regs.h
2061
#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
2256
#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
drivers/gpu/drm/i915/display/intel_display_regs.h
2269
#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
drivers/gpu/drm/i915/display/intel_display_regs.h
2279
#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
drivers/gpu/drm/i915/display/intel_display_regs.h
2295
#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2313
#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19)
drivers/gpu/drm/i915/display/intel_display_regs.h
2319
#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
2338
#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */
drivers/gpu/drm/i915/display/intel_display_regs.h
2340
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
2341
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/i915/display/intel_display_regs.h
2342
#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2352
#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/i915/display/intel_display_regs.h
2354
#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20)
drivers/gpu/drm/i915/display/intel_display_regs.h
2356
#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
drivers/gpu/drm/i915/display/intel_display_regs.h
2361
#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
2367
#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
drivers/gpu/drm/i915/display/intel_display_regs.h
2447
#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
drivers/gpu/drm/i915/display/intel_display_regs.h
2459
#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
drivers/gpu/drm/i915/display/intel_display_regs.h
2491
#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2519
#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
drivers/gpu/drm/i915/display/intel_display_regs.h
2524
#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
drivers/gpu/drm/i915/display/intel_display_regs.h
2527
#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
drivers/gpu/drm/i915/display/intel_display_regs.h
2545
#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/i915/display/intel_display_regs.h
2547
#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2656
#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/i915/display/intel_display_regs.h
2657
#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/display/intel_display_regs.h
2658
#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2660
#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/display/intel_display_regs.h
2661
#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2769
#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
drivers/gpu/drm/i915/display/intel_display_regs.h
2841
#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2843
#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
2884
#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
drivers/gpu/drm/i915/display/intel_display_regs.h
2894
#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
drivers/gpu/drm/i915/display/intel_display_regs.h
2921
#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
drivers/gpu/drm/i915/display/intel_display_regs.h
2945
#define MTL_TRCD_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/display/intel_display_regs.h
2946
#define MTL_TRP_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
2947
#define MTL_DCLK_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
2950
#define MTL_TRAS_MASK REG_GENMASK(16, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
2951
#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
349
#define HTOTAL_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
351
#define HACTIVE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
357
#define HBLANK_END_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
359
#define HBLANK_START_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
365
#define HSYNC_END_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
367
#define HSYNC_START_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
373
#define VTOTAL_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
375
#define VACTIVE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
381
#define VBLANK_END_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
383
#define VBLANK_START_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
389
#define VSYNC_END_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
391
#define VSYNC_START_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
397
#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
399
#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
636
#define DP_PIPE_SEL_MASK REG_GENMASK(30, 30)
drivers/gpu/drm/i915/display/intel_display_regs.h
638
#define DP_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_display_regs.h
641
#define DP_PIPE_SEL_MASK_CHV REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
643
#define DP_LINK_TRAIN_MASK REG_GENMASK(29, 28)
drivers/gpu/drm/i915/display/intel_display_regs.h
648
#define DP_LINK_TRAIN_MASK_CPT REG_GENMASK(10, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
653
#define DP_VOLTAGE_MASK REG_GENMASK(27, 25)
drivers/gpu/drm/i915/display/intel_display_regs.h
658
#define DP_PRE_EMPHASIS_MASK REG_GENMASK(24, 22)
drivers/gpu/drm/i915/display/intel_display_regs.h
663
#define DP_PORT_WIDTH_MASK REG_GENMASK(21, 19)
drivers/gpu/drm/i915/display/intel_display_regs.h
666
#define EDP_PLL_FREQ_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
697
#define TU_SIZE_MASK REG_GENMASK(30, 25)
drivers/gpu/drm/i915/display/intel_display_regs.h
699
#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
728
#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
736
#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
drivers/gpu/drm/i915/display/intel_display_regs.h
741
#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
drivers/gpu/drm/i915/display/intel_display_regs.h
747
#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
drivers/gpu/drm/i915/display/intel_display_regs.h
757
#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
drivers/gpu/drm/i915/display/intel_display_regs.h
758
#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
drivers/gpu/drm/i915/display/intel_display_regs.h
765
#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
drivers/gpu/drm/i915/display/intel_display_regs.h
771
#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
drivers/gpu/drm/i915/display/intel_display_regs.h
776
#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
drivers/gpu/drm/i915/display/intel_display_regs.h
782
#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/display/intel_display_regs.h
787
#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
864
#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
drivers/gpu/drm/i915/display/intel_display_regs.h
870
#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/display/intel_display_regs.h
879
#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/display/intel_display_regs.h
882
#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
drivers/gpu/drm/i915/display/intel_display_regs.h
888
#define UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK REG_GENMASK(29, 24)
drivers/gpu/drm/i915/display/intel_display_regs.h
889
#define UNDERRUN_DDB_EMPTY_MASK REG_GENMASK(21, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
890
#define UNDERRUN_DBUF_NOT_FILLED_MASK REG_GENMASK(13, 8)
drivers/gpu/drm/i915/display/intel_display_regs.h
891
#define UNDERRUN_BELOW_WM0_MASK REG_GENMASK(5, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
897
#define UNDERRUN_PIPE_FRAME_COUNT_MASK REG_GENMASK(30, 20)
drivers/gpu/drm/i915/display/intel_display_regs.h
898
#define UNDERRUN_LINE_COUNT_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
901
#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
902
#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_display_regs.h
915
#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
916
#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_display_regs.h
974
#define CHV_BLEND_MASK REG_GENMASK(31, 30)
drivers/gpu/drm/i915/display/intel_display_regs.h
981
#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
drivers/gpu/drm/i915/display/intel_display_regs.h
982
#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
drivers/gpu/drm/i915/display/intel_display_regs.h
983
#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
152
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3)
drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
154
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5)
drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
61
#define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
304
#define PIPEDMC_SSP REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
305
#define PIPEDMC_INT_VECTOR_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
310
#define PIPEDMC_EVT_PENDING REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
329
#define PIPEDMC_FPQ_PLANEQ_3_TP_MASK REG_GENMASK(31, 26)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
331
#define PIPEDMC_FPQ_PLANEQ_2_TP_MASK REG_GENMASK(24, 19)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
333
#define PIPEDMC_FPQ_PLANEQ_1_TP_MASK REG_GENMASK(17, 12)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
335
#define PIPEDMC_FPQ_FASTQ_TP_MASK REG_GENMASK(10, 6)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
337
#define PIPEDMC_FPQ_GENERALQ_TP_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
352
#define PIPEDMC_SCANLINE_NUMBER REG_GENMASK(20, 0)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
359
#define PIPEDMC_SCANLINE_LOWER_MASK REG_GENMASK(20, 0)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
365
#define PIPEDMC_SCANLINE_UPPER_MASK REG_GENMASK(20, 0)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
494
#define DMC_EVT_CTL_TYPE_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
499
#define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
541
#define PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(26, 24)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
543
#define PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(18, 16)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
545
#define PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
547
#define PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
557
#define LNL_FQ_DSB_ID_MASK REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
560
#define LNL_FQ_DSB_SIZE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
575
#define PTL_FQ_DSB_ID_MASK REG_GENMASK(25, 24)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
577
#define PTL_FQ_DSB_SIZE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
50
#define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26)
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
56
#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK REG_GENMASK(24, 20)
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
58
#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK REG_GENMASK(19, 16) /* pre-skl */
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
71
#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK REG_GENMASK(10, 0) /* pre-skl */
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
73
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK REG_GENMASK(9, 5) /* skl+ */
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
75
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
drivers/gpu/drm/i915/display/intel_dsb_regs.h
27
#define DSB_MMIO_DEAD_CLOCKS_COUNT_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
29
#define DSB_MMIO_CYCLES_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
33
#define DSB_POLL_WAIT_MASK REG_GENMASK(30, 23)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
35
#define DSB_POLL_COUNT_MASK REG_GENMASK(22, 15)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
42
#define DSB_REQARB_SM_STATE_MASK REG_GENMASK(29, 27)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
44
#define DSB_VTDFAULT_ARB_SM_STATE_MASK REG_GENMASK(25, 23)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
45
#define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
47
#define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
49
#define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
50
#define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
51
#define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
52
#define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
70
#define DSB_RM_CLAIM_TIMEOUT_COUNT_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
72
#define DSB_RM_READY_TIMEOUT_VALUE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_dsb_regs.h
77
#define DSB_SCANLINE_FOR_DEWAKE_MASK REG_GENMASK(30, 0)
drivers/gpu/drm/i915/display/intel_dvo_regs.h
18
#define DVO_PIPE_STALL_MASK REG_GENMASK(29, 28)
drivers/gpu/drm/i915/display/intel_dvo_regs.h
24
#define DVO_PRESERVE_MASK REG_GENMASK(25, 24)
drivers/gpu/drm/i915/display/intel_dvo_regs.h
49
#define DVO_SRCDIM_HORIZONTAL_MASK REG_GENMASK(22, 12)
drivers/gpu/drm/i915/display/intel_dvo_regs.h
51
#define DVO_SRCDIM_VERTICAL_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
102
#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
106
#define FBC_DIRTY_RECT_END_LINE_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
108
#define FBC_DIRTY_RECT_START_LINE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
120
#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
132
#define FBC_SYS_CACHE_START_BASE_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
134
#define FBC_SYS_CACHEABLE_RANGE_MASK REG_GENMASK(15, 4)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
136
#define FBC_SYS_CACHE_TAG_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
14
#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
19
#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
21
#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
29
#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
32
#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
38
#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
42
#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
45
#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
drivers/gpu/drm/i915/display/intel_fbc_regs.h
61
#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
drivers/gpu/drm/i915/display/intel_fbc_regs.h
65
#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
drivers/gpu/drm/i915/display/intel_fbc_regs.h
70
#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
74
#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
79
#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
80
#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
83
#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
84
#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/display/intel_fbc_regs.h
87
#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/intel_hdcp_regs.h
250
#define STREAM_TYPE_STATUS_MASK REG_GENMASK(30, 30)
drivers/gpu/drm/i915/display/intel_hdcp_regs.h
266
#define AUTH_STREAM_TYPE_MASK REG_GENMASK(31, 31)
drivers/gpu/drm/i915/display/intel_hti_regs.h
12
#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
drivers/gpu/drm/i915/display/intel_lt_phy.c
1736
d8 = (pll_reg_57 & REG_GENMASK(14, 7)) >> 7;
drivers/gpu/drm/i915/display/intel_lt_phy.c
1742
m2div_int = (pll_reg_3 & REG_GENMASK(14, 5)) >> 5;
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
62
#define XE3PLPD_MACCLK_RATE_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
73
#define XE3LPD_PORT_P2M_ADDR_MASK REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/intel_lvds_regs.h
21
#define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_lvds_regs.h
35
#define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8)
drivers/gpu/drm/i915/display/intel_lvds_regs.h
43
#define LVDS_A3_POWER_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/display/intel_lvds_regs.h
50
#define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/i915/display/intel_lvds_regs.h
58
#define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/display/intel_pfit_regs.h
12
#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
14
#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
19
#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
23
#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
26
#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
32
#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
34
#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
36
#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
37
#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
47
#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
drivers/gpu/drm/i915/display/intel_pfit_regs.h
49
#define PF_FILTER_MASK REG_GENMASK(24, 23)
drivers/gpu/drm/i915/display/intel_pfit_regs.h
58
#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_pfit_regs.h
60
#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_pfit_regs.h
66
#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_pfit_regs.h
68
#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
15
#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28)
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
25
#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
30
#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28)
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
38
#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27)
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
47
#define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28)
drivers/gpu/drm/i915/display/intel_pps_regs.h
30
#define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
drivers/gpu/drm/i915/display/intel_pps_regs.h
35
#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_pps_regs.h
48
#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_pps_regs.h
50
#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
drivers/gpu/drm/i915/display/intel_pps_regs.h
58
#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
drivers/gpu/drm/i915/display/intel_pps_regs.h
64
#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
drivers/gpu/drm/i915/display/intel_pps_regs.h
65
#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_pps_regs.h
69
#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
drivers/gpu/drm/i915/display/intel_pps_regs.h
70
#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_pps_regs.h
74
#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
drivers/gpu/drm/i915/display/intel_pps_regs.h
75
#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
106
#define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29)
drivers/gpu/drm/i915/display/intel_psr_regs.h
114
#define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26)
drivers/gpu/drm/i915/display/intel_psr_regs.h
118
#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK REG_GENMASK(24, 20)
drivers/gpu/drm/i915/display/intel_psr_regs.h
119
#define EDP_PSR_STATUS_COUNT_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_psr_regs.h
125
#define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
131
#define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
15
#define EXITLINE_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
166
#define EDP_MAX_SU_DISABLE_TIME_MASK REG_GENMASK(24, 20)
drivers/gpu/drm/i915/display/intel_psr_regs.h
168
#define EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(14, 13)
drivers/gpu/drm/i915/display/intel_psr_regs.h
172
#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(15, 13)
drivers/gpu/drm/i915/display/intel_psr_regs.h
176
#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(18, 13)
drivers/gpu/drm/i915/display/intel_psr_regs.h
180
#define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11)
drivers/gpu/drm/i915/display/intel_psr_regs.h
184
#define TGL_EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 10)
drivers/gpu/drm/i915/display/intel_psr_regs.h
188
#define EDP_PSR2_TP2_TIME_MASK REG_GENMASK(9, 8)
drivers/gpu/drm/i915/display/intel_psr_regs.h
193
#define EDP_PSR2_FRAME_BEFORE_SU_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/i915/display/intel_psr_regs.h
195
#define EDP_PSR2_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
224
#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
drivers/gpu/drm/i915/display/intel_psr_regs.h
239
#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
drivers/gpu/drm/i915/display/intel_psr_regs.h
241
#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
drivers/gpu/drm/i915/display/intel_psr_regs.h
246
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
drivers/gpu/drm/i915/display/intel_psr_regs.h
248
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
274
#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
289
#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(23, 21)
drivers/gpu/drm/i915/display/intel_psr_regs.h
295
#define ALPM_CTL_ALPM_ENTRY_CHECK_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_psr_regs.h
297
#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK REG_GENMASK(13, 8)
drivers/gpu/drm/i915/display/intel_psr_regs.h
300
#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
305
#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24)
drivers/gpu/drm/i915/display/intel_psr_regs.h
307
#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_psr_regs.h
309
#define ALPM_CTL2_NUMBER_OF_LTTPR_MASK REG_GENMASK(15, 12)
drivers/gpu/drm/i915/display/intel_psr_regs.h
311
#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/i915/display/intel_psr_regs.h
314
#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
32
#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25)
drivers/gpu/drm/i915/display/intel_psr_regs.h
321
#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(25, 20)
drivers/gpu/drm/i915/display/intel_psr_regs.h
323
#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_psr_regs.h
325
#define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
332
#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/i915/display/intel_psr_regs.h
335
#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(20, 16)
drivers/gpu/drm/i915/display/intel_psr_regs.h
337
#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/intel_psr_regs.h
339
#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
37
#define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20)
drivers/gpu/drm/i915/display/intel_psr_regs.h
39
#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/intel_psr_regs.h
46
#define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8)
drivers/gpu/drm/i915/display/intel_psr_regs.h
51
#define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/display/intel_psr_regs.h
53
#define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/i915/display/intel_psr_regs.h
58
#define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_psr_regs.h
74
#define TGL_PSR_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/intel_sbi_regs.h
14
#define SBI_ADDR_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sbi_regs.h
20
#define SBI_CTL_DEST_MASK REG_GENMASK(16, 16)
drivers/gpu/drm/i915/display/intel_sbi_regs.h
23
#define SBI_CTL_OP_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/intel_sbi_regs.h
29
#define SBI_RESPONSE_MASK REG_GENMASK(2, 1)
drivers/gpu/drm/i915/display/intel_sbi_regs.h
32
#define SBI_STATUS_MASK REG_GENMASK(0, 0)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
23
#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
24
#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
25
#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
26
#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
32
#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
33
#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
34
#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
38
#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
44
#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
47
#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
48
#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
53
#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
56
#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
59
#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
60
#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
61
#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
62
#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
65
#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
68
#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
71
#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
72
#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
73
#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
102
#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
104
#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
122
#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
134
#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
156
#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
158
#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
16
#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
164
#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
166
#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
180
#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
189
#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
191
#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
206
#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
212
#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
214
#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
240
#define SP_FORMAT_MASK REG_GENMASK(29, 26)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
25
#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
255
#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
275
#define SP_POS_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
277
#define SP_POS_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
283
#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
285
#define SP_WIDTH_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
299
#define SP_ADDR_MASK REG_GENMASK(31, 12)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
308
#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
310
#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
317
#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
327
#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
329
#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
335
#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
337
#define SP_SH_COS_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
357
#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
359
#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
367
#define SPCSC_C1_MASK REG_GENMASK(30, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
369
#define SPCSC_C0_MASK REG_GENMASK(14, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
375
#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
377
#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
383
#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
385
#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
46
#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
48
#define DVS_POS_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
54
#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
56
#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
70
#define DVS_ADDR_MASK REG_GENMASK(31, 12)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
79
#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
81
#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_sprite_regs.h
96
#define DVS_FILTER_MASK REG_GENMASK(30, 29)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
103
#define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
107
#define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
108
#define DSC_PPS2_PIC_HEIGHT_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
113
#define DSC_PPS3_SLICE_WIDTH_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
114
#define DSC_PPS3_SLICE_HEIGHT_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
119
#define DSC_PPS4_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
120
#define DSC_PPS4_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
127
#define DSC_PPS5_SCALE_DEC_INT_MASK REG_GENMASK(27, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
128
#define DSC_PPS5_SCALE_INC_INT_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
133
#define DSC_PPS6_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
134
#define DSC_PPS6_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
135
#define DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
136
#define DSC_PPS6_INITIAL_SCALE_VALUE_MASK REG_GENMASK(5, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
145
#define DSC_PPS7_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
146
#define DSC_PPS7_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
151
#define DSC_PPS8_INITIAL_OFFSET_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
152
#define DSC_PPS8_FINAL_OFFSET_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
159
#define DSC_PPS9_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
160
#define DSC_PPS9_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
167
#define DSC_PPS10_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
168
#define DSC_PPS10_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
169
#define DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
170
#define DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
179
#define DSC_PPS16_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
180
#define DSC_PPS16_SLICE_PER_LINE_MASK REG_GENMASK(18, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
181
#define DSC_PPS16_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
190
#define DSC_PPS17_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
194
#define DSC_PPS18_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
195
#define DSC_PPS18_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
206
#define DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK REG_GENMASK(31, 20)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
208
#define DSC_SUPS0_SU_PIC_HEIGHT_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
39
#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
93
#define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
95
#define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
97
#define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
99
#define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/intel_vga_regs.h
18
#define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */
drivers/gpu/drm/i915/display/intel_vga_regs.h
22
#define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */
drivers/gpu/drm/i915/display/intel_vga_regs.h
31
#define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */
drivers/gpu/drm/i915/display/intel_vga_regs.h
32
#define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */
drivers/gpu/drm/i915/display/intel_vga_regs.h
33
#define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/display/intel_vga_regs.h
34
#define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
106
#define VRR_VMIN_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
113
#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
115
#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
128
#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
145
#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
152
#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
159
#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
16
#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
17
#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
171
#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
173
#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
179
#define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
32
#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
33
#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
47
#define VRR_DCB_FLIPLINE_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
62
#define VRR_DCB_VMAX_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
87
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
91
#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/intel_vrr_regs.h
99
#define VRR_VMAX_MASK REG_GENMASK(19, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
109
#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
119
#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
121
#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
131
#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
133
#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
160
#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
171
#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
181
#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
183
#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
209
#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
210
#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
235
#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
240
#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
259
#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
266
#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
39
#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
441
#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
442
#define PLANE_WM_BLOCKS_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
48
#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
49
#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
494
#define PLANE_BUF_END_MASK REG_GENMASK(28, 16)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
496
#define PLANE_BUF_START_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
507
#define PLANE_MIN_DBUF_BLOCKS_MASK REG_GENMASK(28, 16)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
509
#define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
581
#define PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
68
#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
74
#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
83
#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
92
#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
96
#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
15
#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
drivers/gpu/drm/i915/display/skl_watermark_regs.h
17
#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
drivers/gpu/drm/i915/display/skl_watermark_regs.h
20
#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
24
#define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
26
#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
28
#define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
40
#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
43
#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(16, 13)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
45
#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
67
#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
69
#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(20, 16)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
71
#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
drivers/gpu/drm/i915/display/skl_watermark_regs.h
77
#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
78
#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
81
#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
84
#define LNL_ADDED_WAKE_TIME_MASK REG_GENMASK(28, 16)
drivers/gpu/drm/i915/display/skl_watermark_regs.h
85
#define LNL_PKG_C_LATENCY_MASK REG_GENMASK(12, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
101
#define DPIO_PCS_TX2MARGIN_MASK REG_GENMASK(15, 13)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
104
#define DPIO_PCS_TX1MARGIN_MASK REG_GENMASK(12, 10)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
113
#define DPIO_PCS_TX2DEEMP_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
116
#define DPIO_PCS_TX1DEEMP_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
123
#define DPIO_TX2_STAGGER_MASK_MASK REG_GENMASK(28, 24)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
132
#define DPIO_TX2_STAGGER_MULT_MASK REG_GENMASK(22, 20)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
134
#define DPIO_TX1_STAGGER_MULT_MASK REG_GENMASK(20, 16)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
136
#define DPIO_TX1_STAGGER_MASK_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
139
#define DPIO_LANESTAGGER_STRAP_MASK REG_GENMASK(4, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
157
#define DPIO_SWING_MARGIN000_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
159
#define DPIO_UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
166
#define DPIO_SWING_MARGIN101_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
171
#define DPIO_SWING_DEEMPH9P5_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
173
#define DPIO_SWING_DEEMPH6P0_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
188
#define DPIO_CHV_M2_DIV_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
192
#define DPIO_CHV_N_DIV_MASK REG_GENMASK(11, 8)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
194
#define DPIO_CHV_M1_DIV_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
199
#define DPIO_CHV_M2_FRAC_DIV_MASK REG_GENMASK(21, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
205
#define DPIO_CHV_FEEDFWD_GAIN_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
209
#define DPIO_CHV_GAIN_CTRL_MASK REG_GENMASK(18, 16)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
211
#define DPIO_CHV_INT_COEFF_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
213
#define DPIO_CHV_PROP_COEFF_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
217
#define DPIO_CHV_TDC_TARGET_CNT_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
221
#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
232
#define CHV_BUFRIGHTENA1_MASK REG_GENMASK(21, 20)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
236
#define CHV_BUFLEFTENA1_MASK REG_GENMASK(23, 22)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
243
#define DPIO_CHV_S1_DIV_MASK REG_GENMASK(23, 21)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
245
#define DPIO_CHV_P1_DIV_MASK REG_GENMASK(15, 13)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
247
#define DPIO_CHV_P2_DIV_MASK REG_GENMASK(12, 8)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
249
#define DPIO_CHV_K_DIV_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
259
#define CHV_BUFLEFTENA2_MASK REG_GENMASK(18, 17) /* CL2 DW1 only */
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
263
#define CHV_BUFRIGHTENA2_MASK REG_GENMASK(20, 19) /* CL2 DW1 only */
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
27
#define DPIO_S1_DIV_MASK REG_GENMASK(30, 28)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
280
#define DPIO_SUS_CLK_CONFIG_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
303
#define DPIO_FRC_LATENCY_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
33
#define DPIO_K_DIV_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
35
#define DPIO_P1_DIV_MASK REG_GENMASK(23, 21)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
37
#define DPIO_P2_DIV_MASK REG_GENMASK(20, 16)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
39
#define DPIO_N_DIV_MASK REG_GENMASK(15, 12)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
42
#define DPIO_M1_DIV_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
44
#define DPIO_M2_DIV_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
49
#define DPIO_PLL_MODESEL_MASK REG_GENMASK(26, 24)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
50
#define DPIO_BIAS_CURRENT_CTL_MASK REG_GENMASK(22, 20) /* always 0x7 */
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
51
#define DPIO_PLL_REFCLK_SEL_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
52
#define DPIO_DRIVER_CTL_MASK REG_GENMASK(15, 12) /* always set to 0x8 */
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
53
#define DPIO_CLK_BIAS_CTL_MASK REG_GENMASK(11, 8) /* always set to 0x5 */
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
86
#define DPIO_PCS_CLK_DATAWIDTH_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/gt/intel_engine_regs.h
127
#define XEHP_BLITTER_SCHEDULING_MODE_MASK REG_GENMASK(12, 11)
drivers/gpu/drm/i915/gt/intel_engine_regs.h
137
#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
drivers/gpu/drm/i915/gt/intel_engine_regs.h
138
#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
drivers/gpu/drm/i915/gt/intel_engine_regs.h
154
#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
drivers/gpu/drm/i915/gt/intel_engine_regs.h
155
#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
drivers/gpu/drm/i915/gt/intel_engine_regs.h
215
#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
drivers/gpu/drm/i915/gt/intel_gpu_commands.h
132
#define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
drivers/gpu/drm/i915/gt/intel_gpu_commands.h
247
#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
drivers/gpu/drm/i915/gt/intel_gpu_commands.h
248
#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
drivers/gpu/drm/i915/gt/intel_gpu_commands.h
260
#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
drivers/gpu/drm/i915/gt/intel_gpu_commands.h
261
#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1008
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1136
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1150
#define THROTTLE_12_5 REG_GENMASK(4, 2)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1165
#define STACKID_CTRL REG_GENMASK(6, 5)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1172
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1189
#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1193
#define COMP_CKN_IN REG_GENMASK(30, 29)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1371
#define MEMSTAT_PSTATE_MASK REG_GENMASK(7, 3)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1427
#define XEHP_CCS_MODE_CSLICE_MASK REG_GENMASK(2, 0) /* CCS0-3 + rsvd */
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1432
#define CHV_FGT_EU_DIS_SS1_R1_MASK REG_GENMASK(31, 28)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1433
#define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1434
#define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1435
#define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1521
#define MTL_GT_L3_EXC_MASK REG_GENMASK(5, 3)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1555
#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1556
#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1587
#define ENGINE1_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
1588
#define ENGINE0_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
26
#define MTL_CAGF_MASK REG_GENMASK(8, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
29
#define MTL_CC_MASK REG_GENMASK(10, 9)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
293
#define VERT_WM_VAL REG_GENMASK(9, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
326
#define RING_FAULT_VADDR_MASK REG_GENMASK(31, 12) /* pre-bdw */
drivers/gpu/drm/i915/gt/intel_gt_regs.h
327
#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */
drivers/gpu/drm/i915/gt/intel_gt_regs.h
329
#define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
33
#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
330
#define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1) /* ivb+ */
drivers/gpu/drm/i915/gt/intel_gt_regs.h
392
#define FAULT_VA_HIGH_BITS REG_GENMASK(3, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
41
#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
435
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
437
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
520
#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
drivers/gpu/drm/i915/gt/intel_gt_regs.h
538
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
586
#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
592
#define GEN12_MEML3_EN_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
595
#define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
596
#define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
602
#define GEN10_F2_S_ENA_MASK REG_GENMASK(27, 22)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
603
#define GEN10_F2_SS_DIS_MASK REG_GENMASK(21, 18)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
604
#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
605
#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
606
#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
611
#define GEN8_EU_DIS0_S1_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
612
#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
613
#define GEN11_EU_DIS_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
615
#define XEHP_EU_ENA_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
618
#define GEN8_EU_DIS1_S2_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
619
#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
622
#define GEN11_GT_S_ENA_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
625
#define GEN8_EU_DIS2_S2_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
633
#define GEN11_GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
634
#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
796
#define GEN6_CAGF_MASK REG_GENMASK(14, 8)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
797
#define HSW_CAGF_MASK REG_GENMASK(13, 7)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
798
#define GEN9_CAGF_MASK REG_GENMASK(31, 23)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
80
#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
81
#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
882
#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
902
#define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
941
#define GEN11_ARBITRATION_PRIO_ORDER_MASK REG_GENMASK(27, 22)
drivers/gpu/drm/i915/gt/intel_gt_regs.h
944
#define GEN11_HASH_CTRL_EXCL_MASK REG_GENMASK(6, 0)
drivers/gpu/drm/i915/gt/intel_gtt.h
158
#define MTL_PPAT_L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/gt/intel_gtt.h
159
#define MTL_PAT_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
186
#define INTEL_GUC_TLB_INVAL_TYPE_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
187
#define INTEL_GUC_TLB_INVAL_MODE_MASK REG_GENMASK(11, 8)
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
168
#define SLPC_MAX_UNSLICE_FREQ_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
169
#define SLPC_MIN_UNSLICE_FREQ_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
170
#define SLPC_MAX_SLICE_FREQ_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
171
#define SLPC_MIN_SLICE_FREQ_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/gvt/handlers.c
794
u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
drivers/gpu/drm/i915/i915_reg.h
1002
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
drivers/gpu/drm/i915/i915_reg.h
1003
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
drivers/gpu/drm/i915/i915_reg.h
1004
#define GMD_ID_STEP REG_GENMASK(5, 0)
drivers/gpu/drm/i915/i915_reg.h
1030
#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
drivers/gpu/drm/i915/i915_reg.h
1081
#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
drivers/gpu/drm/i915/i915_reg.h
1082
#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
drivers/gpu/drm/i915/i915_reg.h
1083
#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
drivers/gpu/drm/i915/i915_reg.h
1102
#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/i915/i915_reg.h
1103
#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/i915_reg.h
1104
#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/i915_reg.h
1105
#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/i915_reg.h
1118
#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/i915_reg.h
1122
#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
drivers/gpu/drm/i915/i915_reg.h
1123
#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
drivers/gpu/drm/i915/i915_reg.h
1132
#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/i915_reg.h
1136
#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/i915/i915_reg.h
1140
#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/i915_reg.h
1142
#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/i915/i915_reg.h
1168
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/i915_reg.h
1214
#define GMS_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/i915_reg.h
1215
#define GGMS_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/i915/i915_reg.h
1231
#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/i915_reg.h
1233
#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
drivers/gpu/drm/i915/i915_reg.h
1237
#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
drivers/gpu/drm/i915/i915_reg.h
1238
#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/i915/i915_reg.h
1239
#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/i915/i915_reg.h
296
#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
drivers/gpu/drm/i915/i915_reg.h
360
#define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/i915/i915_reg.h
587
#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
drivers/gpu/drm/i915/i915_reg.h
592
#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
drivers/gpu/drm/i915/i915_reg.h
737
#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
drivers/gpu/drm/i915/i915_reg.h
738
#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
drivers/gpu/drm/i915/i915_reg.h
742
#define MTL_RPE_MASK REG_GENMASK(8, 0)
drivers/gpu/drm/i915/i915_reg.h
754
#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/i915/i915_reg.h
960
#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
drivers/gpu/drm/i915/i915_reg.h
965
#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
drivers/gpu/drm/i915/i915_reg.h
973
#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
126
#define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11)
drivers/gpu/drm/i915/intel_mchbar_regs.h
127
#define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
129
#define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9)
drivers/gpu/drm/i915/intel_mchbar_regs.h
130
#define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
drivers/gpu/drm/i915/intel_mchbar_regs.h
133
#define SKL_DRAM_DDR_TYPE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
163
#define SKL_DIMM_S_RANK_MASK REG_GENMASK(26, 26)
drivers/gpu/drm/i915/intel_mchbar_regs.h
166
#define SKL_DIMM_S_WIDTH_MASK REG_GENMASK(25, 24)
drivers/gpu/drm/i915/intel_mchbar_regs.h
170
#define SKL_DIMM_S_SIZE_MASK REG_GENMASK(21, 16)
drivers/gpu/drm/i915/intel_mchbar_regs.h
171
#define SKL_DIMM_L_RANK_MASK REG_GENMASK(10, 10)
drivers/gpu/drm/i915/intel_mchbar_regs.h
174
#define SKL_DIMM_L_WIDTH_MASK REG_GENMASK(9, 8)
drivers/gpu/drm/i915/intel_mchbar_regs.h
178
#define SKL_DIMM_L_SIZE_MASK REG_GENMASK(5, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
179
#define ICL_DIMM_S_RANK_MASK REG_GENMASK(27, 26)
drivers/gpu/drm/i915/intel_mchbar_regs.h
182
#define ICL_DIMM_S_WIDTH_MASK REG_GENMASK(25, 24)
drivers/gpu/drm/i915/intel_mchbar_regs.h
186
#define ICL_DIMM_S_SIZE_MASK REG_GENMASK(22, 16)
drivers/gpu/drm/i915/intel_mchbar_regs.h
187
#define ICL_DIMM_L_RANK_MASK REG_GENMASK(10, 9)
drivers/gpu/drm/i915/intel_mchbar_regs.h
192
#define ICL_DIMM_L_WIDTH_MASK REG_GENMASK(8, 7)
drivers/gpu/drm/i915/intel_mchbar_regs.h
196
#define ICL_DIMM_L_SIZE_MASK REG_GENMASK(6, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
199
#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
drivers/gpu/drm/i915/intel_mchbar_regs.h
214
#define PKG_PWR_UNIT REG_GENMASK(3, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
215
#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
drivers/gpu/drm/i915/intel_mchbar_regs.h
216
#define PKG_TIME_UNIT REG_GENMASK(19, 16)
drivers/gpu/drm/i915/intel_mchbar_regs.h
222
#define TEMP_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
226
#define RP0_CAP_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
227
#define RP1_CAP_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/intel_mchbar_regs.h
228
#define RPN_CAP_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/i915/intel_mchbar_regs.h
231
#define RPE_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/i915/intel_mchbar_regs.h
233
#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
235
#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
drivers/gpu/drm/i915/intel_mchbar_regs.h
236
#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
drivers/gpu/drm/i915/intel_mchbar_regs.h
237
#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
drivers/gpu/drm/i915/intel_mchbar_regs.h
247
#define SSKPD_WM3_MASK_SNB REG_GENMASK(29, 24)
drivers/gpu/drm/i915/intel_mchbar_regs.h
248
#define SSKPD_WM2_MASK_SNB REG_GENMASK(21, 16)
drivers/gpu/drm/i915/intel_mchbar_regs.h
249
#define SSKPD_WM1_MASK_SNB REG_GENMASK(13, 8)
drivers/gpu/drm/i915/intel_mchbar_regs.h
250
#define SSKPD_WM0_MASK_SNB REG_GENMASK(5, 0)
drivers/gpu/drm/i915/intel_mchbar_regs.h
82
#define MLTR_WM2_MASK REG_GENMASK(13, 8)
drivers/gpu/drm/i915/intel_mchbar_regs.h
83
#define MLTR_WM1_MASK REG_GENMASK(5, 0)
drivers/gpu/drm/xe/abi/guc_actions_abi.h
275
#define XE_G2G_REGISTER_DEVICE REG_GENMASK(16, 16)
drivers/gpu/drm/xe/abi/guc_actions_abi.h
276
#define XE_G2G_REGISTER_TILE REG_GENMASK(15, 12)
drivers/gpu/drm/xe/abi/guc_actions_abi.h
277
#define XE_G2G_REGISTER_TYPE REG_GENMASK(11, 8)
drivers/gpu/drm/xe/abi/guc_actions_abi.h
278
#define XE_G2G_REGISTER_SIZE REG_GENMASK(7, 0)
drivers/gpu/drm/xe/abi/guc_actions_abi.h
280
#define XE_G2G_DEREGISTER_DEVICE REG_GENMASK(16, 16)
drivers/gpu/drm/xe/abi/guc_actions_abi.h
281
#define XE_G2G_DEREGISTER_TILE REG_GENMASK(15, 12)
drivers/gpu/drm/xe/abi/guc_actions_abi.h
282
#define XE_G2G_DEREGISTER_TYPE REG_GENMASK(11, 8)
drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
168
#define SLPC_MAX_UNSLICE_FREQ_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
169
#define SLPC_MIN_UNSLICE_FREQ_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
170
#define SLPC_MAX_SLICE_FREQ_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
171
#define SLPC_MIN_SLICE_FREQ_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/xe/instructions/xe_gfx_state_commands.h
11
#define GFX_STATE_OPCODE REG_GENMASK(28, 26)
drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
11
#define GFXPIPE_PIPELINE REG_GENMASK(28, 27)
drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
155
#define CMD_3DSTATE_SO_DECL_LIST_DW_LEN REG_GENMASK(8, 0)
drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
17
#define GFXPIPE_OPCODE REG_GENMASK(26, 24)
drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
18
#define GFXPIPE_SUBOPCODE REG_GENMASK(23, 16)
drivers/gpu/drm/xe/instructions/xe_gsc_commands.h
23
#define GSC_OPCODE REG_GENMASK(28, 22)
drivers/gpu/drm/xe/instructions/xe_gsc_commands.h
24
#define GSC_CMD_DATA_AND_LEN REG_GENMASK(21, 0)
drivers/gpu/drm/xe/instructions/xe_mfx_commands.h
11
#define MFX_CMD_SUBTYPE REG_GENMASK(28, 27) /* A.K.A cmd pipe */
drivers/gpu/drm/xe/instructions/xe_mfx_commands.h
12
#define MFX_CMD_OPCODE REG_GENMASK(26, 24)
drivers/gpu/drm/xe/instructions/xe_mfx_commands.h
13
#define MFX_CMD_SUB_OPCODE REG_GENMASK(23, 16)
drivers/gpu/drm/xe/instructions/xe_mfx_commands.h
14
#define MFX_FLAGS_AND_LEN REG_GENMASK(15, 0)
drivers/gpu/drm/xe/instructions/xe_mi_commands.h
18
#define MI_OPCODE REG_GENMASK(28, 23)
drivers/gpu/drm/xe/instructions/xe_mi_commands.h
19
#define MI_SUBOPCODE REG_GENMASK(22, 17) /* used with MI_EXPANSION */
drivers/gpu/drm/xe/instructions/xe_mi_commands.h
61
#define MI_FLUSH_DW_LEN_DW REG_GENMASK(5, 0)
drivers/gpu/drm/xe/instructions/xe_mi_commands.h
81
#define MI_SET_APPID_SESSION_ID_MASK REG_GENMASK(6, 0)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
102
#define SELECTIVE_READ_GROUP REG_GENMASK(29, 23)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
103
#define SELECTIVE_READ_INSTANCE REG_GENMASK(22, 16)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
112
#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 8)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
113
#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 1)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
140
#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 9)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
141
#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 1)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
148
#define IDLE_DELAY REG_GENMASK(20, 0)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
179
#define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
184
#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
185
#define RING_FORCE_TO_NONPRIV_RANGE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
47
#define ENGINE_INSTANCE_ID REG_GENMASK(9, 4)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
48
#define ENGINE_CLASS_ID REG_GENMASK(2, 0)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
51
#define TAIL_ADDR REG_GENMASK(20, 3)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
54
#define HEAD_ADDR REG_GENMASK(20, 2)
drivers/gpu/drm/xe/regs/xe_engine_regs.h
69
#define IDLE_WAIT_TIME REG_GENMASK(19, 0)
drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
12
#define XEHPC_EUSTALL_BASE_BUF_ADDR REG_GENMASK(31, 6)
drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
13
#define XEHPC_EUSTALL_BASE_XECORE_BUF_SZ REG_GENMASK(5, 3)
drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
19
#define XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK REG_GENMASK(15, 2)
drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
23
#define XEHPC_EUSTALL_REPORT1_READ_PTR_MASK REG_GENMASK(15, 2)
drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
26
#define EUSTALL_MOCS REG_GENMASK(9, 3)
drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
27
#define EUSTALL_SAMPLE_RATE REG_GENMASK(2, 0)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
37
#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
52
#define GSCI_TIMER_STATUS_VALUE REG_GENMASK(1, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
111
#define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
125
#define VS_HIT_MAX_VALUE_MASK REG_GENMASK(25, 20)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
137
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
139
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
187
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
206
#define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
209
#define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
21
#define MTL_CAGF_MASK REG_GENMASK(8, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
22
#define MTL_CC_MASK REG_GENMASK(12, 9)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
220
#define CCS_EN_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
221
#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
224
#define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
226
#define XEHPC_GT_L3_MODE_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
227
#define XE2_GT_L3_MODE_MASK REG_GENMASK(7, 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
228
#define L3BANK_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
229
#define XELP_GT_L3_MODE_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
232
#define MEML3_EN_MASK REG_GENMASK(3, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
240
#define XE3_L3BANK_ENABLE REG_GENMASK(31, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
243
#define XELP_EU_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
248
#define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
249
#define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
258
#define FUSE_SERVICE_COPY_ENABLE_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
26
#define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
31
#define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
339
#define REQ_RATIO_MASK REG_GENMASK(31, 23)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
342
#define RPSWCTL_MASK REG_GENMASK(10, 9)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
38
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
39
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
393
#define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
394
#define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
400
#define L3_CACHEABILITY_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
402
#define L3_SCC_MASK REG_GENMASK(3, 1)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
411
#define LSN_LNI_WGT_MASK REG_GENMASK(31, 28)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
413
#define LSN_LNE_WGT_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
415
#define LSN_DIM_X_WGT_MASK REG_GENMASK(23, 20)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
417
#define LSN_DIM_Y_WGT_MASK REG_GENMASK(19, 16)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
419
#define LSN_DIM_Z_WGT_MASK REG_GENMASK(15, 12)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
432
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
45
#define GMD_ID_SUBIP_FLAG_MASK REG_GENMASK(13, 6)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
46
#define GMD_ID_REVID REG_GENMASK(5, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
472
#define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */
drivers/gpu/drm/xe/regs/xe_gt_regs.h
482
#define SMP_WAIT_FETCH_MERGING_COUNTER REG_GENMASK(11, 10)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
502
#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
535
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
557
#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
561
#define COMP_CKN_IN REG_GENMASK(30, 29)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
57
#define MCR_SLICE_MASK REG_GENMASK(30, 27)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
577
#define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */
drivers/gpu/drm/xe/regs/xe_gt_regs.h
59
#define MCR_SUBSLICE_MASK REG_GENMASK(26, 24)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
594
#define RCN_MASK REG_GENMASK(2, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
61
#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
62
#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
626
#define VOLTAGE_MASK REG_GENMASK(10, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
68
#define LE_SSE_MASK REG_GENMASK(18, 17)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
70
#define LE_COS_MASK REG_GENMASK(16, 15)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
73
#define LE_PFM_MASK REG_GENMASK(13, 11)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
75
#define LE_SCC_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
81
#define LE_LRUM_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
83
#define LE_TGT_CACHE_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
85
#define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/xe/regs/xe_gt_regs.h
89
#define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
17
#define DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
18
#define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
30
#define GS_AUTH_STATUS_MASK REG_GENMASK(31, 30)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
33
#define GS_MIA_MASK REG_GENMASK(18, 16)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
37
#define GS_UKERNEL_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
38
#define GS_BOOTROM_MASK REG_GENMASK(7, 1)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
46
#define GUC_WOPCM_SIZE_MASK REG_GENMASK(31, 12)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
50
#define GUC_MOCS_INDEX_MASK REG_GENMASK(27, 24)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
73
#define DMA_ADDR_SPACE_MASK REG_GENMASK(20, 16)
drivers/gpu/drm/xe/regs/xe_guc_regs.h
83
#define GUC_WOPCM_OFFSET_MASK REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
47
#define ENGINE1_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/xe/regs/xe_irq_regs.h
48
#define ENGINE0_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
31
#define PKG_PWR_UNIT REG_GENMASK(3, 0)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
32
#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
33
#define PKG_TIME_UNIT REG_GENMASK(19, 16)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
38
#define TEMP_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
41
#define PWR_LIM_VAL REG_GENMASK(14, 0)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
43
#define PWR_LIM REG_GENMASK(15, 0)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
44
#define PWR_LIM_TIME REG_GENMASK(23, 17)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
45
#define PWR_LIM_TIME_X REG_GENMASK(23, 22)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
46
#define PWR_LIM_TIME_Y REG_GENMASK(21, 17)
drivers/gpu/drm/xe/regs/xe_mert_regs.h
14
#define CATERR_VFID REG_GENMASK(16, 9)
drivers/gpu/drm/xe/regs/xe_mert_regs.h
15
#define CATERR_CODES REG_GENMASK(5, 0)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
24
#define OAR_OACONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
33
#define OAG_OAGLBCTXCTRL_TIMER_PERIOD_MASK REG_GENMASK(7, 2)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
38
#define OAG_OAHEADPTR_MASK REG_GENMASK(31, 6)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
40
#define OAG_OATAILPTR_MASK REG_GENMASK(31, 6)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
43
#define OABUFFER_SIZE_MASK REG_GENMASK(5, 3)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
47
#define OAG_OACONTROL_OA_PES_DISAG_EN REG_GENMASK(27, 22)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
48
#define OAG_OACONTROL_OA_CCS_SELECT_MASK REG_GENMASK(18, 16)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
49
#define OAG_OACONTROL_OA_COUNTER_SEL_MASK REG_GENMASK(4, 2)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
52
#define OA_OACONTROL_REPORT_BC_MASK REG_GENMASK(9, 9)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
53
#define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8)
drivers/gpu/drm/xe/regs/xe_oa_regs.h
84
#define OAM_CONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1)
drivers/gpu/drm/xe/regs/xe_pcode_regs.h
26
#define TEMP_MASK_VRAM_N REG_GENMASK(30, 8)
drivers/gpu/drm/xe/regs/xe_regs.h
29
#define TILE_COUNT REG_GENMASK(15, 8)
drivers/gpu/drm/xe/regs/xe_regs.h
32
#define GMS_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/xe/regs/xe_regs.h
33
#define GGMS_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/xe/regs/xe_regs.h
51
#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
drivers/gpu/drm/xe/regs/xe_regs.h
52
#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
drivers/gpu/drm/xe/regs/xe_regs.h
55
#define MTL_RPA_MASK REG_GENMASK(8, 0)
drivers/gpu/drm/xe/regs/xe_regs.h
58
#define MTL_RPE_MASK REG_GENMASK(8, 0)
drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
11
#define SG_REMAP_TELEM_MASK REG_GENMASK(31, 24)
drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
12
#define SG_REMAP_SYSCTRL_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
219
#define TEMP_MASK REG_GENMASK(10, 8)
drivers/gpu/drm/xe/tests/xe_rtp_test.c
276
XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_GENMASK(1, 0)))
drivers/gpu/drm/xe/xe_guc_fwif.h
46
#define GUC_LOG_CRASH_DUMP REG_GENMASK(5, 4)
drivers/gpu/drm/xe/xe_guc_fwif.h
47
#define GUC_LOG_EVENT_DATA REG_GENMASK(9, 6)
drivers/gpu/drm/xe/xe_guc_fwif.h
48
#define GUC_LOG_STATE_CAPTURE REG_GENMASK(11, 10)
drivers/gpu/drm/xe/xe_guc_fwif.h
49
#define GUC_LOG_BUF_ADDR REG_GENMASK(31, 12)
drivers/gpu/drm/xe/xe_guc_fwif.h
72
#define GUC_LOG_VERBOSITY REG_GENMASK(1, 0)
drivers/gpu/drm/xe/xe_guc_fwif.h
74
#define GUC_LOG_DESTINATION REG_GENMASK(5, 4)
drivers/gpu/drm/xe/xe_guc_fwif.h
79
#define GUC_ADS_ADDR REG_GENMASK(21, 1)
drivers/gpu/drm/xe/xe_guc_pc.c
43
#define RP0_MASK REG_GENMASK(7, 0)
drivers/gpu/drm/xe/xe_guc_pc.c
44
#define RP1_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/xe/xe_guc_pc.c
45
#define RPN_MASK REG_GENMASK(23, 16)
drivers/gpu/drm/xe/xe_guc_pc.c
48
#define RPE_MASK REG_GENMASK(15, 8)
drivers/gpu/drm/xe/xe_guc_pc.c
49
#define RPA_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/xe/xe_guc_pc.c
52
#define CAGF_MASK REG_GENMASK(19, 11)
drivers/gpu/drm/xe/xe_irq.c
507
if (master_ctl == REG_GENMASK(31, 0)) {
drivers/gpu/drm/xe/xe_lrc.c
1874
(*(++dw) & REG_GENMASK(31, 23)) == MI_NOOP)
drivers/gpu/drm/xe/xe_mocs.c
108
#define XE2_L3_CLOS_MASK REG_GENMASK(7, 6)
drivers/gpu/drm/xe/xe_mocs.c
67
#define L3_CACHE_POLICY_MASK REG_GENMASK(5, 4)
drivers/gpu/drm/xe/xe_mocs.c
68
#define L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/xe/xe_pat.c
31
#define XE2_L3_CLOS REG_GENMASK(7, 6)
drivers/gpu/drm/xe/xe_pat.c
32
#define XE2_L3_POLICY REG_GENMASK(5, 4)
drivers/gpu/drm/xe/xe_pat.c
33
#define XE2_L4_POLICY REG_GENMASK(3, 2)
drivers/gpu/drm/xe/xe_pat.c
34
#define XE2_COH_MODE REG_GENMASK(1, 0)
drivers/gpu/drm/xe/xe_pat.c
36
#define XELPG_L4_POLICY_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/xe/xe_pat.c
40
#define XELPG_INDEX_COH_MODE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/xe/xe_pat.c
45
#define XEHPC_CLOS_LEVEL_MASK REG_GENMASK(3, 2)
drivers/gpu/drm/xe/xe_pat.c
48
#define XELP_MEM_TYPE_MASK REG_GENMASK(1, 0)
drivers/gpu/drm/xe/xe_pcode_api.h
102
#define LINK_DOWNGRADE REG_GENMASK(1, 0)
drivers/gpu/drm/xe/xe_pcode_api.h
12
#define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
drivers/gpu/drm/xe/xe_pcode_api.h
13
#define PCODE_MB_PARAM1 REG_GENMASK(15, 8)
drivers/gpu/drm/xe/xe_pcode_api.h
14
#define PCODE_MB_COMMAND REG_GENMASK(7, 0)
drivers/gpu/drm/xe/xe_pcode_api.h
44
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/xe/xe_pcode_api.h
58
#define PCIE_SENSOR_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/xe/xe_pcode_api.h
68
#define MAJOR_VERSION_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/xe/xe_pcode_api.h
69
#define MINOR_VERSION_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/xe/xe_pcode_api.h
70
#define HOTFIX_VERSION_MASK REG_GENMASK(31, 16)
drivers/gpu/drm/xe/xe_pcode_api.h
71
#define BUILD_VERSION_MASK REG_GENMASK(15, 0)
drivers/gpu/drm/xe/xe_pcode_api.h
87
#define BREADCRUMB_VERSION REG_GENMASK(31, 29)
drivers/gpu/drm/xe/xe_pcode_api.h
88
#define AUXINFO_REG_OFFSET REG_GENMASK(17, 15)
drivers/gpu/drm/xe/xe_pcode_api.h
89
#define OVERFLOW_REG_OFFSET REG_GENMASK(14, 12)
drivers/gpu/drm/xe/xe_pcode_api.h
94
#define BOOT_STATUS REG_GENMASK(3, 1)
drivers/gpu/drm/xe/xe_pcode_api.h
99
#define AUXINFO_HISTORY_OFFSET REG_GENMASK(31, 29)
drivers/gpu/drm/xe/xe_reg_whitelist.c
220
range_start = reg & REG_GENMASK(25, range_bit);
drivers/gpu/drm/xe/xe_reg_whitelist.c
221
range_end = range_start | REG_GENMASK(range_bit, 0);
