drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

343

#define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val))

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

346

REG_FIELD_PREP16(C20_PHY_TX_DCC_CAL_RANGE_MASK, (val))

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

349

#define C20_PHY_TX_TERM_CTL(val) REG_FIELD_PREP16(C20_PHY_TX_TERM_CTL_MASK, (val))

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

392

#define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

393

#define MPLL_MULTIPLIER(val) REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

400

#define MPLLB_ANA_FREQ_VCO(val) REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

403

#define MPLL_DIV_MULTIPLIER(val) REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

407

#define CAL_DAC_CODE(val) REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

411

#define CP_INT_GS(val) REG_FIELD_PREP16(CP_INT_GS_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

415

#define CP_PROP_GS(val) REG_FIELD_PREP16(CP_PROP_GS_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

419

#define CP_INT(val) REG_FIELD_PREP16(CP_INT_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

423

#define CP_PROP(val) REG_FIELD_PREP16(CP_PROP_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

427

#define V2I(val) REG_FIELD_PREP16(V2I_MASK, val)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

431

#define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val)