drivers/accel/habanalabs/common/habanalabs.h

2654

(val) << REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1429

(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1432

(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1435

WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1438

WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/soc15_common.h

188

~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

55

~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

63

~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

692

(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

693

(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1351

(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1352

(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));