drivers/accel/habanalabs/common/habanalabs.h

2653

~REG_FIELD_MASK(reg, field)) | \

drivers/accel/habanalabs/gaudi2/gaudi2_masks.h

129

REG_FIELD_MASK(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE, HOP4_PAGE_SIZE)

drivers/accel/habanalabs/gaudi2/gaudi2_masks.h

131

REG_FIELD_MASK(DCORE0_HMMU0_STLB_HOP_CONFIGURATION, ONLY_LARGE_PAGE)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1428

(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1429

(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1432

(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1435

WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1438

WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

323

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

370

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

392

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);

drivers/gpu/drm/amd/amdgpu/soc15_common.h

188

~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

55

~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

63

~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \