REG_DIG_GLB_70
xfi_tphy->base + REG_DIG_GLB_70);
mtk_phy_set_bits(xfi_tphy->base + REG_DIG_GLB_70,
mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70,
mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_70, XTP_PCS_UPDT);
mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70,
mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70,
mtk_phy_clear_bits(xfi_tphy->base + REG_DIG_GLB_70, XTP_PCS_UPDT);