REG_CONTROL
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
outb(info->ctrl_reg, iobase + REG_CONTROL);
timer->control = base + REG_CONTROL;
reg = tda1997x_cec_read(sd, REG_CONTROL & 0xff);
tda1997x_cec_write(sd, REG_CONTROL & 0xff, reg);
writeb(CTRL_RST|CTRL_ACK, REG_CONTROL);
writeb(CTRL_RST|CTRL_ACK, REG_CONTROL);
writeb(CTRL_RST, REG_CONTROL);
writeb(0, REG_CONTROL);
writeb(CTRL_CA, REG_CONTROL);
writeb(CTRL_CA, REG_CONTROL);
writeb(CTRL_CA | CTRL_ACK, REG_CONTROL);
writeb(CTRL_CA, REG_CONTROL);
writeb(CTRL_CA, REG_CONTROL);
writeb(CTRL_ACK, REG_CONTROL);
ret = regmap_write(tps->regmap, REG_CONTROL, 0xE0);
ret = regmap_write(tps->regmap, REG_CONTROL, 0x0);
__func__, REG_CONTROL, ret);
u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
ctrl = readl_relaxed(qspi->regs + REG_CONTROL);
control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
control = readl_relaxed(qspi->regs + REG_CONTROL);
u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
writel_relaxed(control, qspi->regs + REG_CONTROL);
u32 control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
u32 control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
u32 control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
mpfs_spi_write(spi, REG_CONTROL, control);
u32 control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
mpfs_spi_write(spi, REG_CONTROL, control);
control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
u32 control = mpfs_spi_read(spi, REG_CONTROL);
mpfs_spi_write(spi, REG_CONTROL, control);
mpfs_spi_write(spi, REG_CONTROL, control);
mpfs_spi_write(spi, REG_CONTROL, control);