REG_CLR_BIT
REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
REG_CLR_BIT(ah, AR_PHY_TIMING_CTRL4(0),
REG_CLR_BIT(ah, AR9285_AN_RF2G6, 1 << 0);
REG_CLR_BIT(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL);
REG_CLR_BIT(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB);
REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL);
REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1);
REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2);
REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT);
REG_CLR_BIT(ah, 0x9808, 1 << 27);
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_FLTR_CAL);
REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);
REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit);
REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
REG_CLR_BIT(ah, AR_BTCOEX_RC, 0x1);
REG_CLR_BIT(ah, AR_PHY_TIMING4,
REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah),
REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah),
REG_CLR_BIT(ah, AR_PHY_CHAN_INFO_MEMORY(ah),
REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah),
REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
REG_CLR_BIT(ah, AR_PHY_RESTART,
REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
REG_CLR_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR);
REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
REG_CLR_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_WOW_PME_CLR);
REG_CLR_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN);
REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5));
REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah),
REG_CLR_BIT(ah, AR_BT_COEX_MODE2, AR_BT_PHY_ERR_BT_COLL_ENABLE);
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF);
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);
REG_CLR_BIT(ah, AR_RTC_RESET(ah), AR_RTC_RESET_EN);
REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);
REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
REG_CLR_BIT(ah, AR_IMR_S5,
REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
REG_CLR_BIT(ah, AR_DIAG_SW,
REG_CLR_BIT(ah, AR_DIAG_SW,
REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
REG_CLR_BIT(ah, AR_PHY_TEST(ah), AR_PHY_TEST_RX_OBS_SEL_BIT5);