arch/arm/mach-imx/anatop.c

46

REG_SET : REG_CLR;

arch/arm/mach-imx/anatop.c

52

regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),

arch/arm/mach-imx/anatop.c

58

regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),

arch/arm/mach-imx/anatop.c

64

regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),

drivers/gpu/drm/mxsfb/lcdif_kms.c

398

writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_drv.c

173

writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_drv.c

185

writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_drv.c

186

writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

216

writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

239

writel(mask, addr + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

257

writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

270

writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

429

writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

440

writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

441

writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);

drivers/misc/rp1/rp1_pci.c

52

iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq));

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

154

regmap_write(priv->regmap, PHY_CTRL + REG_CLR,

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

157

regmap_write(priv->regmap, PHY_CTRL + REG_CLR,

drivers/thermal/imx91_thermal.c

127

writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR);

drivers/thermal/imx91_thermal.c

130

writel_relaxed(IMX91_TMU_THR_CTRL01_THR1_MASK, tmu->base + IMX91_TMU_THR_CTRL01 + REG_CLR);

drivers/thermal/imx91_thermal.c

135

writel_relaxed(IMX91_TMU_STAT0_THR1_IF, tmu->base + IMX91_TMU_STAT0 + REG_CLR);

drivers/thermal/imx91_thermal.c

183

writel(IMX91_TMU_STAT0_THR1_IF, tmu->base + IMX91_TMU_STAT0 + REG_CLR);

drivers/thermal/imx91_thermal.c

184

writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR);

drivers/thermal/imx91_thermal.c

212

tmu->base + IMX91_TMU_CTRL0 + REG_CLR);

drivers/thermal/imx91_thermal.c

218

writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR);

drivers/thermal/imx91_thermal.c

289

tmu->base + IMX91_TMU_CTRL1 + REG_CLR);

drivers/thermal/imx91_thermal.c

293

writel_relaxed(IMX91_TMU_CTRL1_MEAS_MODE_MASK, tmu->base + IMX91_TMU_CTRL1 + REG_CLR);

drivers/thermal/imx91_thermal.c

92

reg += enable ? REG_SET : REG_CLR;

drivers/thermal/imx_thermal.c

228

regmap_write(map, soc_data->panic_alarm_ctrl + REG_CLR,

drivers/thermal/imx_thermal.c

248

regmap_write(map, soc_data->high_alarm_ctrl + REG_CLR,

drivers/thermal/imx_thermal.c

615

regmap_write(map, IMX6_MISC1 + REG_CLR,

drivers/thermal/imx_thermal.c

646

regmap_write(map, data->socdata->sensor_ctrl + REG_CLR,

drivers/thermal/imx_thermal.c

648

regmap_write(map, data->socdata->sensor_ctrl + REG_CLR,

drivers/thermal/imx_thermal.c

650

regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR,

drivers/thermal/imx_thermal.c

702

regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR,

drivers/thermal/imx_thermal.c

712

regmap_write(map, data->socdata->sensor_ctrl + REG_CLR,

drivers/thermal/imx_thermal.c

806

ret = regmap_write(map, socdata->sensor_ctrl + REG_CLR,

drivers/thermal/imx_thermal.c

832

ret = regmap_write(map, socdata->sensor_ctrl + REG_CLR,