RCPU_DIV_CFG_REG
RCPU_DIV_CFG_REG, 0, 1, CLK_SET_RATE_NO_REPARENT);
RCPU_DIV_CFG_REG, 2, 4, 0, 0);
RCPU_DIV_CFG_REG, 7, 4, 0, 0);
RCPU_DIV_CFG_REG, 12, 6, 0, 0);