REG_ADDR
writeb(ireg, p->regs + REG_ADDR);
writeb(ireg, p->regs + REG_ADDR);
ret = regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_data);
ret = regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_data);
ret = regmap_read(data->regmap, REG_ADDR(ch->address), val);
ret = regmap_write(data->regmap, REG_ADDR(ch->address), val);
SET_REG_BITS(&val, REG_ADDR, reg);
SET_REG_BITS(&val, REG_ADDR, reg);
addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
writel_relaxed((u32)val, REG_ADDR(bp, offset))
writew_relaxed((u16)val, REG_ADDR(bp, offset))
#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START);
#define OFFSET(REG_ADDR) (REG_ADDR << 2)
#define OFFSET(REG_ADDR) ((REG_ADDR) << 2)
#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset);
val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
err = idt82p33_write(idt82p33, REG_ADDR(page, loaddr),
#define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))