REGV_RD32
u32 reg = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX;
u32 reg = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX;
u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX;
u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN);
u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX;
return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM);
return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);
u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);
val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY);
val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN);
u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);
u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY);
u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE);
u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV);
u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);
val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC);
u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);
u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);
u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);
val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);
u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG);
val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);
val = REGV_RD32(IVPU_MMU_REG_IDR0);
val = REGV_RD32(IVPU_MMU_REG_IDR1);
val = REGV_RD32(IVPU_MMU_REG_IDR3);
val = REGV_RD32(IVPU_MMU_REG_IDR5);
val = REGV_RD32(IVPU_MMU_REG_CMDQ_CONS);
evtq->prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC);
u32 val = REGV_RD32(IVPU_MMU_REG_CR0);
vdev->mmu->evtq.cons = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC);
vdev->mmu->evtq.prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC);
gerror_val = REGV_RD32(IVPU_MMU_REG_GERROR);
gerrorn_val = REGV_RD32(IVPU_MMU_REG_GERRORN);