REGSTORE
REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23));
REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23));
REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) & ~(1 << irqidx));
REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) | (1 << irqidx));
REGSTORE(regs->cfg_stat, priv->pci_area & 0xf0000000);
REGSTORE(regs->page1, ahbadr);
REGSTORE(regs->iomap, REGLOAD(regs->iomap) & 0x0000ffff);
REGSTORE(regs->irq, 0);
REGSTORE(regs->page1, 0xffffffff);
REGSTORE(regs->irq, err_mask);
REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
REGSTORE(regs->ctrl, CTRL_RESET);
REGSTORE(regs->ctrl, 0);
REGSTORE(regs->sts_cap, ~0); /* Clear Status */
REGSTORE(regs->dma_ctrl, 0);
REGSTORE(regs->dma_bdbase, 0);
REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
REGSTORE(regs->ahbmst_map[i], priv->pci_area);
REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);