REGISTER_PLL_DIV
[BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
[BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
[BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
[BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
[BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
[BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
[BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
[BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
[BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
[BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
[BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
[BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
[BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
[BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
[BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV(
static struct rp1_clk_desc pll_video_sec_desc = REGISTER_PLL_DIV(
static struct rp1_clk_desc pll_audio_sec_desc = REGISTER_PLL_DIV(
static struct rp1_clk_desc pll_audio_tern_desc = REGISTER_PLL_DIV(