REGISTERS_BASE
[ACX_REG_INTERRUPT_TRIG] = (REGISTERS_BASE + 0x0474),
[ACX_REG_INTERRUPT_TRIG_H] = (REGISTERS_BASE + 0x0478),
[ACX_REG_INTERRUPT_MASK] = (REGISTERS_BASE + 0x0494),
[ACX_REG_HINT_MASK_SET] = (REGISTERS_BASE + 0x0498),
[ACX_REG_HINT_MASK_CLR] = (REGISTERS_BASE + 0x049C),
[ACX_REG_INTERRUPT_NO_CLEAR] = (REGISTERS_BASE + 0x04B0),
[ACX_REG_INTERRUPT_CLEAR] = (REGISTERS_BASE + 0x04A4),
[ACX_REG_INTERRUPT_ACK] = (REGISTERS_BASE + 0x04A8),
[ACX_REG_SLV_SOFT_RESET] = (REGISTERS_BASE + 0x0000),
[ACX_REG_EE_START] = (REGISTERS_BASE + 0x080C),
[ACX_REG_ECPU_CONTROL] = (REGISTERS_BASE + 0x0804)
if (addr < REGISTERS_BASE) {
wl1251_set_partition(wl, 0, 0, REGISTERS_BASE, REGISTERS_DOWN_SIZE);
REGISTERS_BASE,
#define SOR_CFG (REGISTERS_BASE + 0x0800)
#define ECPU_CTRL (REGISTERS_BASE + 0x0804)
#define HI_CFG (REGISTERS_BASE + 0x0808)
#define EE_START (REGISTERS_BASE + 0x080C)
#define EE_CTL (REGISTERS_BASE + 0x2000)
#define EE_CTL (REGISTERS_BASE + 0x2000)
#define EE_DATA (REGISTERS_BASE + 0x2004)
#define EE_ADDR (REGISTERS_BASE + 0x2008)
#define EE_ADDR (REGISTERS_BASE + 0x2008)
#define EE_DATA (REGISTERS_BASE + 0x2004)
#define CHIP_ID_B (REGISTERS_BASE + 0x5674)
#define ENABLE (REGISTERS_BASE + 0x5450)
#define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
#define ELP_CMD (REGISTERS_BASE + 0x5808)
#define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
#define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
#define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
#define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
#define SCR_PAD0 (REGISTERS_BASE + 0x5608)
#define SCR_PAD1 (REGISTERS_BASE + 0x560C)
#define SCR_PAD2 (REGISTERS_BASE + 0x5610)
#define SCR_PAD3 (REGISTERS_BASE + 0x5614)
#define SCR_PAD4 (REGISTERS_BASE + 0x5618)
#define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
#define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
#define SCR_PAD5 (REGISTERS_BASE + 0x5624)
#define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
#define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
#define SCR_PAD6 (REGISTERS_BASE + 0x5630)
#define SCR_PAD7 (REGISTERS_BASE + 0x5634)
#define SCR_PAD8 (REGISTERS_BASE + 0x5638)
#define SCR_PAD9 (REGISTERS_BASE + 0x563C)
#define SPARE_A1 (REGISTERS_BASE + 0x0994)
#define SPARE_A2 (REGISTERS_BASE + 0x0998)
#define SPARE_A3 (REGISTERS_BASE + 0x099C)
#define SPARE_A4 (REGISTERS_BASE + 0x09A0)
#define SPARE_A5 (REGISTERS_BASE + 0x09A4)
#define SPARE_A6 (REGISTERS_BASE + 0x09A8)
#define SPARE_A7 (REGISTERS_BASE + 0x09AC)
#define SPARE_A8 (REGISTERS_BASE + 0x09B0)
#define SPARE_B1 (REGISTERS_BASE + 0x5420)
#define SPARE_B2 (REGISTERS_BASE + 0x5424)
#define SPARE_B3 (REGISTERS_BASE + 0x5428)
#define SPARE_B4 (REGISTERS_BASE + 0x542C)
#define SPARE_B5 (REGISTERS_BASE + 0x5430)
#define SPARE_B6 (REGISTERS_BASE + 0x5434)
#define SPARE_B7 (REGISTERS_BASE + 0x5438)
#define SPARE_B8 (REGISTERS_BASE + 0x543C)
#define WL1251_PART_DOWN_REG_START REGISTERS_BASE
#define WL1251_PART_WORK_REG_START REGISTERS_BASE
.start = REGISTERS_BASE,
.start = REGISTERS_BASE,
.start = REGISTERS_BASE,
#define WL12XX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
#define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
#define WL12XX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
#define WL12XX_REG_RX_DRIVER_COUNTER (REGISTERS_BASE + 0x0538)
#define SOR_CFG (REGISTERS_BASE + 0x0800)
#define WL12XX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
#define WL12XX_HI_CFG (REGISTERS_BASE + 0x0808)
#define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
#define WL12XX_OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
#define WL12XX_OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
#define WL12XX_OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
#define WL12XX_OCP_CMD (REGISTERS_BASE + 0x09C0)
#define WL12XX_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
#define WL12XX_CHIP_ID_B (REGISTERS_BASE + 0x5674)
#define WL12XX_ENABLE (REGISTERS_BASE + 0x5450)
#define WL12XX_ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
#define WL12XX_ELP_CMD (REGISTERS_BASE + 0x5808)
#define WL12XX_PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
#define WL12XX_CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
#define WL12XX_CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
#define WL12XX_CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
#define WL12XX_SCR_PAD0 (REGISTERS_BASE + 0x5608)
#define WL12XX_SCR_PAD1 (REGISTERS_BASE + 0x560C)
#define WL12XX_SCR_PAD2 (REGISTERS_BASE + 0x5610)
#define WL12XX_SCR_PAD3 (REGISTERS_BASE + 0x5614)
#define WL12XX_SCR_PAD4 (REGISTERS_BASE + 0x5618)
#define WL12XX_SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
#define WL12XX_SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
#define WL12XX_SCR_PAD5 (REGISTERS_BASE + 0x5624)
#define WL12XX_SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
#define WL12XX_SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
#define WL12XX_SCR_PAD6 (REGISTERS_BASE + 0x5630)
#define WL12XX_SCR_PAD7 (REGISTERS_BASE + 0x5634)
#define WL12XX_SCR_PAD8 (REGISTERS_BASE + 0x5638)
#define WL12XX_SCR_PAD9 (REGISTERS_BASE + 0x563C)
#define WL12XX_SPARE_A1 (REGISTERS_BASE + 0x0994)
#define WL12XX_SPARE_A2 (REGISTERS_BASE + 0x0998)
#define WL12XX_SPARE_A3 (REGISTERS_BASE + 0x099C)
#define WL12XX_SPARE_A4 (REGISTERS_BASE + 0x09A0)
#define WL12XX_SPARE_A5 (REGISTERS_BASE + 0x09A4)
#define WL12XX_SPARE_A6 (REGISTERS_BASE + 0x09A8)
#define WL12XX_SPARE_A7 (REGISTERS_BASE + 0x09AC)
#define WL12XX_SPARE_A8 (REGISTERS_BASE + 0x09B0)
#define WL12XX_SPARE_B1 (REGISTERS_BASE + 0x5420)
#define WL12XX_SPARE_B2 (REGISTERS_BASE + 0x5424)
#define WL12XX_SPARE_B3 (REGISTERS_BASE + 0x5428)
#define WL12XX_SPARE_B4 (REGISTERS_BASE + 0x542C)
#define WL12XX_SPARE_B5 (REGISTERS_BASE + 0x5430)
#define WL12XX_SPARE_B6 (REGISTERS_BASE + 0x5434)
#define WL12XX_SPARE_B7 (REGISTERS_BASE + 0x5438)
#define WL12XX_SPARE_B8 (REGISTERS_BASE + 0x543C)
#define WL12XX_PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
#define WL12XX_WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
#define WL12XX_WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)
#define WL12XX_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
#define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
#define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
#define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
#define WL12XX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
#define WL12XX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
#define WL12XX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
#define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
#define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)