REG3
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
ldx [REG1 + 0x08], REG3; \
add REG2, REG3, REG3; \
cmp VADDR, REG3; \
ldx [REG1 + 0x10], REG3; \
add REG3, REG2, REG1; \
#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
TSB_LOAD_QUAD(REG2, REG3); \
cmp REG3, TAG; \
#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
TSB_LOAD_QUAD(REG2, REG3); \
cmp REG3, TAG; \
append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
append_math_add_imm_u32(desc, REG3, ZERO, IMM, assoclen);
append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, ivsize);
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG3, CAAM_CMD_SZ);
append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, REG3, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM,
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3,
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, ivsize);
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
ACT88xx_REG("REG3", ACT8846, REG3, VSET0, "vp3"),