REG1
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
lduh [THR + TI_CPU], REG1; \
sllx REG1, TRAP_BLOCK_SZ_SHIFT, REG1; \
add REG2, REG1, REG2; \
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
661: casa [TSB] ASI_N, REG1, REG2; \
casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
#define TSB_CAS_TAG(TSB, REG1, REG2) \
661: casxa [TSB] ASI_N, REG1, REG2; \
casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
#define TSB_LOCK_TAG(TSB, REG1, REG2) \
99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
andcc REG1, REG2, %g0; \
TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
cmp REG1, REG2; \
#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
sethi %hi(swapper_pg_dir), REG1; \
or REG1, %lo(swapper_pg_dir), REG1; \
ldx [REG1 + REG2], REG1; \
brz,pn REG1, FAIL_LABEL; \
ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
brz,pn REG1, FAIL_LABEL; \
brz,pn REG1, FAIL_LABEL; \
andcc REG1, REG2, %g0; \
ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
brz,pn REG1, FAIL_LABEL; \
andcc REG1, REG2, %g0; \
697: brgez,pn REG1, FAIL_LABEL; \
andn REG1, REG2, REG1; \
or REG1, REG2, REG1; \
ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
brgez,pn REG1, FAIL_LABEL; \
#define USER_PGTABLE_CHECK_PUD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
brz,pn REG1, FAIL_LABEL; \
andcc REG1, REG2, %g0; \
brgez,pn REG1, FAIL_LABEL; \
andn REG1, REG2, REG1; \
brlz,pt REG1, PTE_LABEL; \
or REG1, REG2, REG1; \
#define USER_PGTABLE_CHECK_PUD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
brz,pn REG1, FAIL_LABEL; \
#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
brz,pn REG1, FAIL_LABEL; \
andcc REG1, REG2, %g0; \
brgez,pn REG1, FAIL_LABEL; \
andn REG1, REG2, REG1; \
brlz,pt REG1, PTE_LABEL; \
or REG1, REG2, REG1; \
#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
brz,pn REG1, FAIL_LABEL; \
#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
ldxa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
brz,pn REG1, FAIL_LABEL; \
ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
USER_PGTABLE_CHECK_PUD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
brz,pn REG1, FAIL_LABEL; \
ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
add REG1, REG2, REG1; \
ldxa [REG1] ASI_PHYS_USE_EC, REG1; \
brgez,pn REG1, FAIL_LABEL; \
#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
sethi %hi(prom_trans), REG1; \
or REG1, %lo(prom_trans), REG1; \
97: ldx [REG1 + 0x00], REG2; \
ldx [REG1 + 0x08], REG3; \
ldx [REG1 + 0x10], REG3; \
add REG3, REG2, REG1; \
add REG1, (3 * 8), REG1; \
#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
661: sethi %uhi(swapper_tsb), REG1; \
or REG1, %ulo(swapper_tsb), REG1; \
sllx REG1, 32, REG1; \
or REG1, REG2, REG1; \
add REG1, REG2, REG2; \
mov REG4, REG1;
#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
661: sethi %uhi(swapper_4m_tsb), REG1; \
or REG1, %ulo(swapper_4m_tsb), REG1; \
sllx REG1, 32, REG1; \
or REG1, REG2, REG1; \
add REG1, REG2, REG2; \
mov REG4, REG1;
#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
*cs++ = CS_ALU_INSTR_LOADINV(SRCB, REG1);
#define MKREQ(REG0, REG1, SIZE, ...) \
REG0, REG1, SIZE, \
ACT88xx_REG("REG1", ACT8846, REG1, VSET, "vp1"),
PRINT_MIS_word(asd_ha, REG1);
REG1(io_port);
REG1(base);
REG1(base);
REG1(port_base);
REG1;
REG1;
REG1;
REG1;
REG1;
REG1;
REG1;
x = sbus_readl(dbri->regs + REG1);