REG0
append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, REG3, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0,
append_math_add(desc, VARSEQINLEN, SEQOUTLEN, REG0,
append_math_add(desc, VARSEQOUTLEN, SEQOUTLEN, REG0,
append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG0,
append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, VARSEQOUTLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
*cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0);
*cs++ = CS_ALU_INSTR_STORE(REG0, ACCU);
*cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0);
*cs++ = CS_ALU_INSTR_STORE(REG0, ACCU);
#define MKREQ(REG0, REG1, SIZE, ...) \
REG0, REG1, SIZE, \
ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
PRINT_MIS_word(asd_ha, REG0);
REG0(port_base);
REG0(port_base);
REG0(port_base);
REG0(port_base);
REG0;
REG0;
REG0;
REG0;
REG0;
REG0;
REG0;
REG0;
tmp = sbus_readl(dbri->regs + REG0);
sbus_writel(tmp, dbri->regs + REG0);
tmp = sbus_readl(dbri->regs + REG0);
sbus_writel(tmp, dbri->regs + REG0);
tmp = sbus_readl(dbri->regs + REG0);
sbus_writel(tmp, dbri->regs + REG0);
tmp = sbus_readl(dbri->regs + REG0);
sbus_writel(tmp, dbri->regs + REG0);
tmp = sbus_readl(dbri->regs + REG0);
sbus_writel(tmp, dbri->regs + REG0);
snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
tmp = sbus_readl(dbri->regs + REG0);
sbus_writel(tmp, dbri->regs + REG0);
sbus_readl(dbri->regs + REG0),
sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
tmp = sbus_readl(dbri->regs + REG0);
sbus_writel(tmp, dbri->regs + REG0);