Symbol: REG
arch/arm64/include/asm/hw_breakpoint.h
102
#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
arch/arm64/include/asm/hw_breakpoint.h
103
write_sysreg(VAL, dbg##REG##N##_el1);\
arch/arm64/include/asm/hw_breakpoint.h
98
#define AARCH64_DBG_READ(N, REG, VAL) do {\
arch/arm64/include/asm/hw_breakpoint.h
99
VAL = read_sysreg(dbg##REG##N##_el1);\
arch/arm64/kernel/hw_breakpoint.c
100
WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
101
WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
102
WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
103
WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
104
WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
105
WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
arch/arm64/kernel/hw_breakpoint.c
61
#define READ_WB_REG_CASE(OFF, N, REG, VAL) \
arch/arm64/kernel/hw_breakpoint.c
63
AARCH64_DBG_READ(N, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
66
#define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
arch/arm64/kernel/hw_breakpoint.c
68
AARCH64_DBG_WRITE(N, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
71
#define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
arch/arm64/kernel/hw_breakpoint.c
72
READ_WB_REG_CASE(OFF, 0, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
73
READ_WB_REG_CASE(OFF, 1, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
74
READ_WB_REG_CASE(OFF, 2, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
75
READ_WB_REG_CASE(OFF, 3, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
76
READ_WB_REG_CASE(OFF, 4, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
77
READ_WB_REG_CASE(OFF, 5, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
78
READ_WB_REG_CASE(OFF, 6, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
79
READ_WB_REG_CASE(OFF, 7, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
80
READ_WB_REG_CASE(OFF, 8, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
81
READ_WB_REG_CASE(OFF, 9, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
82
READ_WB_REG_CASE(OFF, 10, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
83
READ_WB_REG_CASE(OFF, 11, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
84
READ_WB_REG_CASE(OFF, 12, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
85
READ_WB_REG_CASE(OFF, 13, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
86
READ_WB_REG_CASE(OFF, 14, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
87
READ_WB_REG_CASE(OFF, 15, REG, VAL)
arch/arm64/kernel/hw_breakpoint.c
89
#define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \
arch/arm64/kernel/hw_breakpoint.c
90
WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
91
WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
92
WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
93
WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
94
WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
95
WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
96
WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
97
WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
98
WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \
arch/arm64/kernel/hw_breakpoint.c
99
WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \
arch/arm64/kvm/hyp/nvhe/sys_regs.c
363
#define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 }
arch/arm64/kvm/hyp/nvhe/sys_regs.c
366
#define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 }
arch/arm64/kvm/hyp/nvhe/sys_regs.c
379
#define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi }
arch/arm64/kvm/hyp/nvhe/sys_regs.c
382
#define HOST_HANDLED(REG) { SYS_DESC(REG), .access = NULL }
arch/loongarch/include/asm/hw_breakpoint.h
57
#define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \
arch/loongarch/include/asm/hw_breakpoint.h
60
VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \
arch/loongarch/include/asm/hw_breakpoint.h
62
VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \
arch/loongarch/include/asm/hw_breakpoint.h
65
#define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \
arch/loongarch/include/asm/hw_breakpoint.h
68
csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \
arch/loongarch/include/asm/hw_breakpoint.h
70
csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \
arch/loongarch/include/uapi/asm/kvm.h
92
#define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 | (REG << LOONGARCH_REG_SHIFT))
arch/loongarch/include/uapi/asm/kvm.h
93
#define KVM_IOC_CSRID(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CSR, REG)
arch/loongarch/include/uapi/asm/kvm.h
94
#define KVM_IOC_CPUCFG(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CPUCFG, REG)
arch/loongarch/kernel/hw_breakpoint.c
36
#define READ_WB_REG_CASE(OFF, N, REG, T, VAL) \
arch/loongarch/kernel/hw_breakpoint.c
38
LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
41
#define WRITE_WB_REG_CASE(OFF, N, REG, T, VAL) \
arch/loongarch/kernel/hw_breakpoint.c
43
LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
46
#define GEN_READ_WB_REG_CASES(OFF, REG, T, VAL) \
arch/loongarch/kernel/hw_breakpoint.c
47
READ_WB_REG_CASE(OFF, 0, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
48
READ_WB_REG_CASE(OFF, 1, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
49
READ_WB_REG_CASE(OFF, 2, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
50
READ_WB_REG_CASE(OFF, 3, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
51
READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
52
READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
53
READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
54
READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
55
READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
56
READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
57
READ_WB_REG_CASE(OFF, 10, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
58
READ_WB_REG_CASE(OFF, 11, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
59
READ_WB_REG_CASE(OFF, 12, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
60
READ_WB_REG_CASE(OFF, 13, REG, T, VAL);
arch/loongarch/kernel/hw_breakpoint.c
62
#define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \
arch/loongarch/kernel/hw_breakpoint.c
63
WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
64
WRITE_WB_REG_CASE(OFF, 1, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
65
WRITE_WB_REG_CASE(OFF, 2, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
66
WRITE_WB_REG_CASE(OFF, 3, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
67
WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
68
WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
69
WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
70
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
71
WRITE_WB_REG_CASE(OFF, 8, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
72
WRITE_WB_REG_CASE(OFF, 9, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
73
WRITE_WB_REG_CASE(OFF, 10, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
74
WRITE_WB_REG_CASE(OFF, 11, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
75
WRITE_WB_REG_CASE(OFF, 12, REG, T, VAL); \
arch/loongarch/kernel/hw_breakpoint.c
76
WRITE_WB_REG_CASE(OFF, 13, REG, T, VAL);
arch/mips/kvm/trace.h
143
#define KVM_TRACE_COP0(REG, SEL) ((KVM_TRACE_HWR_COP0 << 8) | \
arch/mips/kvm/trace.h
144
((REG) << 3) | (SEL))
arch/mips/kvm/trace.h
145
#define KVM_TRACE_HWR(REG, SEL) ((KVM_TRACE_HWR_HWR << 8) | \
arch/mips/kvm/trace.h
146
((REG) << 3) | (SEL))
arch/powerpc/include/asm/reg.h
1240
#define MTFSF_L(REG) \
arch/powerpc/include/asm/reg.h
1241
.long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
arch/powerpc/include/asm/reg.h
1243
#define MTFSF_L(REG) mtfsf 0xff, (REG)
arch/powerpc/kernel/process.c
1536
printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
arch/powerpc/kernel/process.c
1540
printk("MSR: "REG" ", regs->msr);
arch/powerpc/kernel/process.c
1545
pr_cont("CFAR: "REG" ", regs->orig_gpr3);
arch/powerpc/kernel/process.c
1550
pr_cont("DEAR: "REG" ESR: "REG" ", regs->dear, regs->esr);
arch/powerpc/kernel/process.c
1552
pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
arch/powerpc/kernel/process.c
1566
pr_cont(REG " ", regs->gpr[i]);
arch/powerpc/kernel/process.c
1574
printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
arch/powerpc/kernel/process.c
1575
printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
arch/powerpc/kernel/process.c
2314
printk("%s["REG"] ["REG"] %pS",
arch/powerpc/mm/ptdump/ptdump.c
178
pt_dump_seq_printf(st->seq, REG "-" REG " ", st->start_address, addr - 1);
arch/powerpc/mm/ptdump/ptdump.c
179
pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa);
arch/powerpc/xmon/xmon.c
1427
printf("csum stopped at "REG"\n", adrs+i);
arch/powerpc/xmon/xmon.c
1478
printf(" data "REG" [", dabr[i].address);
arch/powerpc/xmon/xmon.c
1754
printf("["REG"] ", sp);
arch/powerpc/xmon/xmon.c
1760
printf("["REG"] ", sp);
arch/powerpc/xmon/xmon.c
1883
printf("*** Error reading registers from "REG"\n",
arch/powerpc/xmon/xmon.c
1898
printf("R%.2d = "REG"%s", n, fp->gpr[n],
arch/powerpc/xmon/xmon.c
1910
printf("msr = "REG" cr = %.8lx\n", fp->msr, fp->ccr);
arch/powerpc/xmon/xmon.c
1911
printf("ctr = "REG" xer = "REG" trap = %4lx\n",
arch/powerpc/xmon/xmon.c
1917
printf("dar = "REG" dsisr = %.8lx\n", fp->dar, fp->dsisr);
arch/powerpc/xmon/xmon.c
2159
printf("msr = "REG" sprg0 = "REG"\n",
arch/powerpc/xmon/xmon.c
2161
printf("pvr = "REG" sprg1 = "REG"\n",
arch/powerpc/xmon/xmon.c
2163
printf("dec = "REG" sprg2 = "REG"\n",
arch/powerpc/xmon/xmon.c
2165
printf("sp = "REG" sprg3 = "REG"\n", sp, mfspr(SPRN_SPRG3));
arch/powerpc/xmon/xmon.c
2166
printf("toc = "REG" dar = "REG"\n", toc, mfspr(SPRN_DAR));
arch/powerpc/xmon/xmon.c
2278
printf("*** Error writing address "REG"\n", adrs + n);
arch/powerpc/xmon/xmon.c
2425
printf(REG"%c", adrs, brev? 'r': ' ');
arch/powerpc/xmon/xmon.c
2847
printf(REG, addr);
arch/powerpc/xmon/xmon.c
2850
printf("\nFaulted reading %d bytes from 0x"REG"\n", 16, addr);
arch/powerpc/xmon/xmon.c
2966
printf(REG, adrs);
arch/powerpc/xmon/xmon.c
3017
printf(REG" %s%s%s%s\n", adr, x, x, x, x);
arch/powerpc/xmon/xmon.c
3031
printf(REG" %08lx", adr, ppc_inst_as_ulong(inst));
arch/powerpc/xmon/xmon.c
3711
printf(REG, address);
arch/sparc/include/asm/asm.h
14
#define BRANCH_REG_ZERO(PREDICT, REG, DEST) \
arch/sparc/include/asm/asm.h
15
brz,PREDICT REG, DEST
arch/sparc/include/asm/asm.h
16
#define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \
arch/sparc/include/asm/asm.h
17
brz,a,PREDICT REG, DEST
arch/sparc/include/asm/asm.h
18
#define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \
arch/sparc/include/asm/asm.h
19
brnz,PREDICT REG, DEST
arch/sparc/include/asm/asm.h
20
#define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \
arch/sparc/include/asm/asm.h
21
brnz,a,PREDICT REG, DEST
arch/sparc/include/asm/asm.h
27
#define BRANCH_REG_ZERO(PREDICT, REG, DEST) \
arch/sparc/include/asm/asm.h
28
cmp REG, 0; \
arch/sparc/include/asm/asm.h
30
#define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \
arch/sparc/include/asm/asm.h
31
cmp REG, 0; \
arch/sparc/include/asm/asm.h
33
#define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \
arch/sparc/include/asm/asm.h
34
cmp REG, 0; \
arch/sparc/include/asm/asm.h
36
#define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \
arch/sparc/include/asm/asm.h
37
cmp REG, 0; \
arch/sparc/include/asm/trap_block.h
120
#define __GET_CPUID(REG) \
arch/sparc/include/asm/trap_block.h
122
661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
arch/sparc/include/asm/trap_block.h
123
srlx REG, 17, REG; \
arch/sparc/include/asm/trap_block.h
124
and REG, 0x1f, REG; \
arch/sparc/include/asm/trap_block.h
130
ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
arch/sparc/include/asm/trap_block.h
131
srlx REG, 17, REG; \
arch/sparc/include/asm/trap_block.h
132
and REG, 0x3ff, REG; \
arch/sparc/include/asm/trap_block.h
135
ldxa [%g0] ASI_JBUS_CONFIG, REG; \
arch/sparc/include/asm/trap_block.h
136
srlx REG, 17, REG; \
arch/sparc/include/asm/trap_block.h
137
and REG, 0x1f, REG; \
arch/sparc/include/asm/trap_block.h
140
sethi %hi(0x1fff40000d0 >> 9), REG; \
arch/sparc/include/asm/trap_block.h
141
sllx REG, 9, REG; \
arch/sparc/include/asm/trap_block.h
142
or REG, 0xd0, REG; \
arch/sparc/include/asm/trap_block.h
143
lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
arch/sparc/include/asm/trap_block.h
145
mov SCRATCHPAD_CPUID, REG; \
arch/sparc/include/asm/trap_block.h
146
ldxa [REG] ASI_SCRATCHPAD, REG; \
arch/sparc/include/asm/tsb.h
77
#define TSB_LOAD_QUAD(TSB, REG) \
arch/sparc/include/asm/tsb.h
78
661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
arch/sparc/include/asm/tsb.h
81
ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
arch/sparc/include/asm/tsb.h
82
ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
arch/sparc/include/asm/tsb.h
85
#define TSB_LOAD_TAG_HIGH(TSB, REG) \
arch/sparc/include/asm/tsb.h
86
661: lduwa [TSB] ASI_N, REG; \
arch/sparc/include/asm/tsb.h
89
lduwa [TSB] ASI_PHYS_USE_EC, REG; \
arch/sparc/include/asm/tsb.h
92
#define TSB_LOAD_TAG(TSB, REG) \
arch/sparc/include/asm/tsb.h
93
661: ldxa [TSB] ASI_N, REG; \
arch/sparc/include/asm/tsb.h
96
ldxa [TSB] ASI_PHYS_USE_EC, REG; \
arch/sparc/kernel/pci_schizo.c
78
#define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
arch/sparc/kernel/pci_schizo.c
81
((unsigned long)(REG)))
arch/sparc/kernel/prom_irqtrans.c
103
#define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
arch/sparc/kernel/prom_irqtrans.c
106
((unsigned long)(REG)))
arch/sparc/kernel/psycho_common.h
15
#define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
arch/sparc/kernel/psycho_common.h
18
((unsigned long)(REG)))
arch/sparc/net/bpf_jit_comp_32.c
121
#define emit_clear(REG) \
arch/sparc/net/bpf_jit_comp_32.c
123
*prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
arch/sparc/net/bpf_jit_comp_32.c
126
#define emit_set_const(K, REG) \
arch/sparc/net/bpf_jit_comp_32.c
128
*prog++ = SETHI(K, REG); \
arch/sparc/net/bpf_jit_comp_32.c
130
*prog++ = OR_LO(K, REG); \
arch/sparc/net/bpf_jit_comp_32.c
220
#define emit_load_cpu(REG) \
arch/sparc/net/bpf_jit_comp_32.c
221
emit_load32(G6, struct thread_info, cpu, REG)
arch/sparc/net/bpf_jit_comp_32.c
223
#define emit_load_cpu(REG) emit_clear(REG)
arch/sparc/net/bpf_jit_comp_32.c
258
#define emit_read_y(REG) *prog++ = RD_Y | RD(REG)
arch/sparc/net/bpf_jit_comp_32.c
259
#define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0)
arch/sparc/net/bpf_jit_comp_32.c
68
#define SETHI(K, REG) \
arch/sparc/net/bpf_jit_comp_32.c
69
(F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
arch/sparc/net/bpf_jit_comp_32.c
70
#define OR_LO(K, REG) \
arch/sparc/net/bpf_jit_comp_32.c
71
(F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
arch/sparc/net/bpf_jit_comp_64.c
136
#define SETHI(K, REG) \
arch/sparc/net/bpf_jit_comp_64.c
137
(F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
arch/sparc/net/bpf_jit_comp_64.c
138
#define OR_LO(K, REG) \
arch/sparc/net/bpf_jit_comp_64.c
139
(F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
arch/sparc/net/bpf_jit_comp_64.c
643
#define emit_read_y(REG, CTX) emit(RD_Y | RD(REG), CTX)
arch/sparc/net/bpf_jit_comp_64.c
644
#define emit_write_y(REG, CTX) emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX)
drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h
284
#define MMU_OFFSET(REG) (REG - mmDCORE0_HMMU0_MMU_BASE)
drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h
300
#define STLB_OFFSET(REG) (REG - mmDCORE0_HMMU0_STLB_BASE)
drivers/accel/ivpu/ivpu_hw_reg_io.h
102
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%016llx\n", func, name, reg, val);
drivers/accel/ivpu/ivpu_hw_reg_io.h
110
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%08x\n", func, name, reg, val);
drivers/accel/ivpu/ivpu_hw_reg_io.h
118
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%016llx\n", func, name, reg, val);
drivers/accel/ivpu/ivpu_hw_reg_io.h
129
ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val);
drivers/accel/ivpu/ivpu_hw_reg_io.h
32
#define REG_FLD(REG, FLD) \
drivers/accel/ivpu/ivpu_hw_reg_io.h
33
(REG##_##FLD##_MASK)
drivers/accel/ivpu/ivpu_hw_reg_io.h
34
#define REG_FLD_NUM(REG, FLD, num) \
drivers/accel/ivpu/ivpu_hw_reg_io.h
35
FIELD_PREP(REG##_##FLD##_MASK, num)
drivers/accel/ivpu/ivpu_hw_reg_io.h
36
#define REG_GET_FLD(REG, FLD, val) \
drivers/accel/ivpu/ivpu_hw_reg_io.h
37
FIELD_GET(REG##_##FLD##_MASK, val)
drivers/accel/ivpu/ivpu_hw_reg_io.h
38
#define REG_CLR_FLD(REG, FLD, val) \
drivers/accel/ivpu/ivpu_hw_reg_io.h
39
((val) & ~(REG##_##FLD##_MASK))
drivers/accel/ivpu/ivpu_hw_reg_io.h
40
#define REG_SET_FLD(REG, FLD, val) \
drivers/accel/ivpu/ivpu_hw_reg_io.h
41
((val) | (REG##_##FLD##_MASK))
drivers/accel/ivpu/ivpu_hw_reg_io.h
42
#define REG_SET_FLD_NUM(REG, FLD, num, val) \
drivers/accel/ivpu/ivpu_hw_reg_io.h
43
(((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))
drivers/accel/ivpu/ivpu_hw_reg_io.h
44
#define REG_TEST_FLD(REG, FLD, val) \
drivers/accel/ivpu/ivpu_hw_reg_io.h
45
((REG##_##FLD##_MASK) == ((val) & (REG##_##FLD##_MASK)))
drivers/accel/ivpu/ivpu_hw_reg_io.h
46
#define REG_TEST_FLD_NUM(REG, FLD, num, val) \
drivers/accel/ivpu/ivpu_hw_reg_io.h
47
((num) == FIELD_GET(REG##_##FLD##_MASK, val))
drivers/accel/ivpu/ivpu_hw_reg_io.h
69
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s started (exp_val 0x%x)\n",
drivers/accel/ivpu/ivpu_hw_reg_io.h
80
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s %s (reg_val 0x%08x)\n",
drivers/accel/ivpu/ivpu_hw_reg_io.h
92
ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%08x\n", func, name, reg, val);
drivers/block/swim.c
44
REG(write_data)
drivers/block/swim.c
45
REG(write_mark)
drivers/block/swim.c
46
REG(write_CRC)
drivers/block/swim.c
47
REG(write_parameter)
drivers/block/swim.c
48
REG(write_phase)
drivers/block/swim.c
49
REG(write_setup)
drivers/block/swim.c
50
REG(write_mode0)
drivers/block/swim.c
51
REG(write_mode1)
drivers/block/swim.c
53
REG(read_data)
drivers/block/swim.c
54
REG(read_mark)
drivers/block/swim.c
55
REG(read_error)
drivers/block/swim.c
56
REG(read_parameter)
drivers/block/swim.c
57
REG(read_phase)
drivers/block/swim.c
58
REG(read_setup)
drivers/block/swim.c
59
REG(read_status)
drivers/block/swim.c
60
REG(read_handshake)
drivers/block/swim.c
69
REG(ph0L)
drivers/block/swim.c
70
REG(ph0H)
drivers/block/swim.c
71
REG(ph1L)
drivers/block/swim.c
72
REG(ph1H)
drivers/block/swim.c
73
REG(ph2L)
drivers/block/swim.c
74
REG(ph2H)
drivers/block/swim.c
75
REG(ph3L)
drivers/block/swim.c
76
REG(ph3H)
drivers/block/swim.c
77
REG(mtrOff)
drivers/block/swim.c
78
REG(mtrOn)
drivers/block/swim.c
79
REG(intDrive)
drivers/block/swim.c
80
REG(extDrive)
drivers/block/swim.c
81
REG(q6L)
drivers/block/swim.c
82
REG(q6H)
drivers/block/swim.c
83
REG(q7L)
drivers/block/swim.c
84
REG(q7H)
drivers/block/swim3.c
63
REG(data);
drivers/block/swim3.c
64
REG(timer); /* counts down at 1MHz */
drivers/block/swim3.c
65
REG(error);
drivers/block/swim3.c
66
REG(mode);
drivers/block/swim3.c
67
REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
drivers/block/swim3.c
68
REG(setup);
drivers/block/swim3.c
69
REG(control); /* writing bits clears them */
drivers/block/swim3.c
70
REG(status); /* writing bits sets them in control */
drivers/block/swim3.c
71
REG(intr);
drivers/block/swim3.c
72
REG(nseek); /* # tracks to seek */
drivers/block/swim3.c
73
REG(ctrack); /* current track number */
drivers/block/swim3.c
74
REG(csect); /* current sector number */
drivers/block/swim3.c
75
REG(gap3); /* size of gap 3 in track format */
drivers/block/swim3.c
76
REG(sector); /* sector # to read or write */
drivers/block/swim3.c
77
REG(nsect); /* # sectors to read or write */
drivers/block/swim3.c
78
REG(intr_enable);
drivers/clk/clk-lochnagar.c
84
#define LN1_CLK(ID, NAME, REG) \
drivers/clk/clk-lochnagar.c
87
.cfg_reg = LOCHNAGAR1_##REG, \
drivers/gpio/gpio-it87.c
102
outb(LDNREG, REG);
drivers/gpio/gpio-it87.c
108
outb(reg, REG);
drivers/gpio/gpio-it87.c
114
outb(reg, REG);
drivers/gpio/gpio-it87.c
122
outb(reg++, REG);
drivers/gpio/gpio-it87.c
124
outb(reg, REG);
drivers/gpio/gpio-it87.c
83
if (!request_muxed_region(REG, 2, KBUILD_MODNAME))
drivers/gpio/gpio-it87.c
86
outb(0x87, REG);
drivers/gpio/gpio-it87.c
87
outb(0x01, REG);
drivers/gpio/gpio-it87.c
88
outb(0x55, REG);
drivers/gpio/gpio-it87.c
89
outb(0x55, REG);
drivers/gpio/gpio-it87.c
95
outb(0x02, REG);
drivers/gpio/gpio-it87.c
97
release_region(REG, 2);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
144
if (REG(REFCLK_CNTL))
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
153
if (REG(REFCLK_CNTL))
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
385
if (REG(DSCCLK3_DTO_PARAM)) {
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
429
if (REG(DSCCLK3_DTO_PARAM)) {
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
132
if (REG(AUX_RESET_MASK)) {
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
143
if (REG(AUX_RESET_MASK)) {
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
197
if (REG(AUXN_IMPCAL)) {
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
1001
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
250
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
262
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
267
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
315
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
689
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
701
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
706
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
741
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
963
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
966
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
969
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
177
if (REG(DCFE_MEM_PWR_CTRL))
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
209
if (REG(DCFE_MEM_PWR_CTRL))
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
327
ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
468
if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
520
if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
236
if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) {
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
249
if (REG(DPG_PIPE_LOW_POWER_CONTROL)) {
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
286
if (REG(DPG_PIPE_STUTTER_CONTROL2))
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
304
if (REG(DPG_PIPE_STUTTER_CONTROL2))
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
332
if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) {
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
130
if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
137
if (REG(AFMT_VBI_PACKET_CONTROL1)) {
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
1381
if (REG(AFMT_CNTL) == 0)
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
230
if (REG(HDMI_GENERIC_PACKET_CONTROL2))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
237
if (REG(HDMI_GENERIC_PACKET_CONTROL2))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
244
if (REG(HDMI_GENERIC_PACKET_CONTROL3))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
251
if (REG(HDMI_GENERIC_PACKET_CONTROL3))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
332
if (REG(DP_MSA_MISC))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
384
if (REG(DP_MSA_TIMING_PARAM1)) {
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
443
if (REG(DP_MSA_COLORIMETRY))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
446
if (REG(DP_MSA_MISC))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
452
if (REG(DP_MSA_TIMING_PARAM1))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
477
if (REG(DP_MSA_TIMING_PARAM2))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
482
if (REG(DP_MSA_TIMING_PARAM3))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
494
if (REG(DP_MSA_TIMING_PARAM4))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
73
if (REG(AFMT_CNTL))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
737
if (REG(AFMT_CNTL))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
76
if (REG(AFMT_VBI_PACKET_CONTROL1)) {
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
775
if (REG(HDMI_DB_CONTROL))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
810
if (REG(HDMI_GENERIC_PACKET_CONTROL2))
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
819
if (REG(HDMI_GENERIC_PACKET_CONTROL3))
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1423
if (REG(DCFE_MEM_PWR_CTRL))
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1431
if (REG(DCFE_MEM_PWR_STATUS)) {
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1477
if (REG(DCFE_MEM_PWR_CTRL))
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1581
if (REG(DCFE_MEM_PWR_CTRL))
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
227
if (REG(DCFE_MEM_PWR_CTRL)) {
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
261
if (REG(DCFE_MEM_PWR_CTRL))
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
236
if (!REG(DP_DPHY_INTERNAL_CTRL))
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
381
if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1371
if (REG(AFMT_CNTL) == 0)
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
125
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
126
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
135
gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
136
gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
145
gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
146
gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
203
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
204
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
213
gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
214
gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
223
gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
224
gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
288
gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
289
gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
293
gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
294
gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
442
gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
443
gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
444
gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
445
gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMA_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
446
gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMA_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
447
gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
448
gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
449
gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
450
gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
451
gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
452
gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
453
gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
454
gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
455
gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
471
gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
472
gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
473
gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
474
gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMB_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
475
gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMB_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
476
gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
477
gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
478
gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
479
gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
480
gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
481
gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
482
gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
483
gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
484
gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
545
gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
546
gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
550
gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
551
gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
595
gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
596
gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
597
gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
598
gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMB_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
599
gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMB_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
600
gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
601
gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
602
gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
603
gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
604
gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
605
gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
606
gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
607
gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
608
gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
624
gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
625
gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
626
gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
627
gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMA_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
628
gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMA_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
629
gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
630
gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
631
gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
632
gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
633
gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
634
gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
635
gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
636
gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
637
gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
549
if (REG(SCL_VERT_FILTER_INIT_BOT)) {
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
565
if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
672
if (REG(SCL_BLACK_OFFSET)) {
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
195
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
196
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
198
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
199
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
256
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
257
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
264
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
265
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
346
icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
347
icsc_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
351
icsc_regs.csc_c11_c12 = REG(CM_ICSC_B_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
352
icsc_regs.csc_c33_c34 = REG(CM_ICSC_B_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
450
gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
451
gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
452
gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
453
gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
454
gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
455
gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
456
gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
457
gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
458
gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
459
gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
460
gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
461
gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
462
gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
463
gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
478
gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
479
gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
480
gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
481
gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
482
gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
483
gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
484
gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
485
gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
486
gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
487
gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
488
gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
489
gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
490
gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
491
gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
157
gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
158
gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
162
gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
163
gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
67
if (REG(CM_SHAPER_CONTROL))
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
69
if (REG(CM_3DLUT_MODE))
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
71
if (REG(CM_3DLUT_READ_WRITE_CONTROL))
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
724
gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
725
gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
726
gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
727
gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
728
gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
729
gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
73
if (REG(CM_3DLUT_MODE))
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
730
gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
731
gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
732
gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
733
gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
734
gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
735
gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
736
gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
737
gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
752
gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
753
gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
754
gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
755
gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
756
gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
757
gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
758
gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
759
gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
760
gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
761
gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
762
gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
763
gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
764
gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
765
gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
77
if (REG(CM_BLNDGAM_CONTROL)) {
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
244
gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
245
gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
246
gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
247
gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
248
gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
249
gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
250
gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
251
gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
252
gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
253
gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMB_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
254
gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMB_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
255
gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMB_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
256
gam_regs.region_start = REG(CM_GAMCOR_RAMB_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
257
gam_regs.region_end = REG(CM_GAMCOR_RAMB_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
259
gam_regs.offset_b = REG(CM_GAMCOR_RAMB_OFFSET_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
260
gam_regs.offset_g = REG(CM_GAMCOR_RAMB_OFFSET_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
261
gam_regs.offset_r = REG(CM_GAMCOR_RAMB_OFFSET_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
262
gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
263
gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
264
gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMB_START_BASE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
266
gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMA_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
267
gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMA_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
268
gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMA_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
269
gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
270
gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
271
gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
272
gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMA_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
273
gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMA_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
274
gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMA_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
275
gam_regs.start_end_cntl2_g = REG(CM_GAMCOR_RAMA_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
276
gam_regs.start_end_cntl1_r = REG(CM_GAMCOR_RAMA_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
277
gam_regs.start_end_cntl2_r = REG(CM_GAMCOR_RAMA_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
278
gam_regs.region_start = REG(CM_GAMCOR_RAMA_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
279
gam_regs.region_end = REG(CM_GAMCOR_RAMA_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
281
gam_regs.offset_b = REG(CM_GAMCOR_RAMA_OFFSET_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
282
gam_regs.offset_g = REG(CM_GAMCOR_RAMA_OFFSET_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
283
gam_regs.offset_r = REG(CM_GAMCOR_RAMA_OFFSET_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
284
gam_regs.start_base_cntl_b = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
285
gam_regs.start_base_cntl_g = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
286
gam_regs.start_base_cntl_r = REG(CM_GAMCOR_RAMA_START_BASE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
348
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
349
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
358
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
359
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
427
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
428
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
435
gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
436
gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
218
cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_A);
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
219
cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_A);
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
221
cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
222
cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_B);
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1146
if (REG(SCL_BLACK_OFFSET)) {
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
546
if (REG(SCL_VERT_FILTER_INIT_BOT)) {
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
556
if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
596
if (REG(SCL_VERT_FILTER_INIT_BOT)) {
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
612
if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
100
gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMA_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
101
gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMA_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
102
gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMA_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
103
gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMA_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
104
gam_regs.offset_b = REG(DWB_OGAM_RAMA_OFFSET_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
105
gam_regs.offset_g = REG(DWB_OGAM_RAMA_OFFSET_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
106
gam_regs.offset_r = REG(DWB_OGAM_RAMA_OFFSET_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
107
gam_regs.region_start = REG(DWB_OGAM_RAMA_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
108
gam_regs.region_end = REG(DWB_OGAM_RAMA_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
122
gam_regs.start_cntl_b = REG(DWB_OGAM_RAMB_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
123
gam_regs.start_cntl_g = REG(DWB_OGAM_RAMB_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
124
gam_regs.start_cntl_r = REG(DWB_OGAM_RAMB_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
125
gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMB_START_BASE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
126
gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMB_START_BASE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
127
gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMB_START_BASE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
128
gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
129
gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
130
gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
131
gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMB_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
132
gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMB_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
133
gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMB_END_CNTL1_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
134
gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMB_END_CNTL2_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
135
gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMB_END_CNTL1_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
136
gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMB_END_CNTL2_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
137
gam_regs.offset_b = REG(DWB_OGAM_RAMB_OFFSET_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
138
gam_regs.offset_g = REG(DWB_OGAM_RAMB_OFFSET_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
139
gam_regs.offset_r = REG(DWB_OGAM_RAMB_OFFSET_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
140
gam_regs.region_start = REG(DWB_OGAM_RAMB_REGION_0_1);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
141
gam_regs.region_end = REG(DWB_OGAM_RAMB_REGION_32_33);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
325
gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPA_C11_C12);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
326
gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPA_C33_C34);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
334
gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPB_C11_C12);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
335
gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPB_C33_C34);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
89
gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
90
gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
91
gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
92
gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
93
gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
94
gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
95
gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
96
gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
97
gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
98
gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMA_END_CNTL1_B);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
99
gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMA_END_CNTL2_B);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
126
case REG(DC_GPIO_SYNCA_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
141
case REG(DC_GPIO_GENLK_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
165
case REG(DC_GPIO_DDC1_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
168
case REG(DC_GPIO_DDC2_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
171
case REG(DC_GPIO_DDC3_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
174
case REG(DC_GPIO_DDC4_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
177
case REG(DC_GPIO_DDC5_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
180
case REG(DC_GPIO_DDC6_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
183
case REG(DC_GPIO_DDCVGA_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
187
case REG(DC_GPIO_I2CPAD_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
191
case REG(DC_GPIO_PWRSEQ_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
192
case REG(DC_GPIO_PAD_STRENGTH_1):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
193
case REG(DC_GPIO_PAD_STRENGTH_2):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
194
case REG(DC_GPIO_DEBUG):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
215
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
218
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
221
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
224
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
227
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
230
info->offset = REG(DC_GPIO_DDC6_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
233
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
236
info->offset = REG(DC_GPIO_I2CPAD_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
247
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
250
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
253
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
256
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
259
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
262
info->offset = REG(DC_GPIO_DDC6_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
265
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
268
info->offset = REG(DC_GPIO_I2CPAD_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
276
info->offset = REG(DC_GPIO_GENERIC_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
305
info->offset = REG(DC_GPIO_HPD_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
333
info->offset = REG(DC_GPIO_SYNCA_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
337
info->offset = REG(DC_GPIO_SYNCA_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
350
info->offset = REG(DC_GPIO_GENLK_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
354
info->offset = REG(DC_GPIO_GENLK_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
359
info->offset = REG(DC_GPIO_GENLK_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
363
info->offset = REG(DC_GPIO_GENLK_A);
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
69
case REG(DC_GPIO_GENERIC_A):
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
99
case REG(DC_GPIO_HPD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
126
case REG(DC_GPIO_SYNCA_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
141
case REG(DC_GPIO_GENLK_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
165
case REG(DC_GPIO_DDC1_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
168
case REG(DC_GPIO_DDC2_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
171
case REG(DC_GPIO_DDC3_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
174
case REG(DC_GPIO_DDC4_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
177
case REG(DC_GPIO_DDC5_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
180
case REG(DC_GPIO_DDC6_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
183
case REG(DC_GPIO_DDCVGA_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
187
case REG(DC_GPIO_I2CPAD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
191
case REG(DC_GPIO_PWRSEQ_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
192
case REG(DC_GPIO_PAD_STRENGTH_1):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
193
case REG(DC_GPIO_PAD_STRENGTH_2):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
194
case REG(DC_GPIO_DEBUG):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
215
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
218
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
221
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
224
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
227
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
230
info->offset = REG(DC_GPIO_DDC6_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
233
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
236
info->offset = REG(DC_GPIO_I2CPAD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
247
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
250
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
253
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
256
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
259
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
262
info->offset = REG(DC_GPIO_DDC6_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
265
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
268
info->offset = REG(DC_GPIO_I2CPAD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
276
info->offset = REG(DC_GPIO_GENERIC_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
305
info->offset = REG(DC_GPIO_HPD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
333
info->offset = REG(DC_GPIO_SYNCA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
337
info->offset = REG(DC_GPIO_SYNCA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
350
info->offset = REG(DC_GPIO_GENLK_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
354
info->offset = REG(DC_GPIO_GENLK_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
359
info->offset = REG(DC_GPIO_GENLK_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
363
info->offset = REG(DC_GPIO_GENLK_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
69
case REG(DC_GPIO_GENERIC_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
99
case REG(DC_GPIO_HPD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
103
case REG(DC_GPIO_HPD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
130
case REG(DC_GPIO_GENLK_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
155
case REG(DC_GPIO_DDC1_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
158
case REG(DC_GPIO_DDC2_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
161
case REG(DC_GPIO_DDC3_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
164
case REG(DC_GPIO_DDC4_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
167
case REG(DC_GPIO_DDC5_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
170
case REG(DC_GPIO_DDC6_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
173
case REG(DC_GPIO_DDCVGA_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
204
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
207
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
210
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
213
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
216
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
219
info->offset = REG(DC_GPIO_DDC6_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
222
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
234
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
237
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
240
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
243
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
246
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
249
info->offset = REG(DC_GPIO_DDC6_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
252
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
261
info->offset = REG(DC_GPIO_GENERIC_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
290
info->offset = REG(DC_GPIO_HPD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
73
case REG(DC_GPIO_GENERIC_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
102
case REG(DC_GPIO_HPD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
129
case REG(DC_GPIO_GENLK_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
154
case REG(DC_GPIO_DDC1_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
157
case REG(DC_GPIO_DDC2_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
160
case REG(DC_GPIO_DDC3_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
163
case REG(DC_GPIO_DDC4_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
166
case REG(DC_GPIO_DDC5_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
169
case REG(DC_GPIO_DDCVGA_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
200
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
203
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
206
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
209
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
212
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
215
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
227
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
230
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
233
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
236
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
239
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
242
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
251
info->offset = REG(DC_GPIO_GENERIC_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
280
info->offset = REG(DC_GPIO_HPD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
72
case REG(DC_GPIO_GENERIC_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
108
case REG(DC_GPIO_HPD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
135
case REG(DC_GPIO_GENLK_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
160
case REG(DC_GPIO_DDC1_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
163
case REG(DC_GPIO_DDC2_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
166
case REG(DC_GPIO_DDC3_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
169
case REG(DC_GPIO_DDC4_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
172
case REG(DC_GPIO_DDC5_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
175
case REG(DC_GPIO_DDC6_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
178
case REG(DC_GPIO_DDCVGA_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
209
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
212
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
215
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
218
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
221
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
224
info->offset = REG(DC_GPIO_DDC6_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
227
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
239
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
242
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
245
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
248
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
251
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
254
info->offset = REG(DC_GPIO_DDC6_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
257
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
266
info->offset = REG(DC_GPIO_GENERIC_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
295
info->offset = REG(DC_GPIO_HPD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
78
case REG(DC_GPIO_GENERIC_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
103
case REG(DC_GPIO_HPD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
130
case REG(DC_GPIO_GENLK_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
155
case REG(DC_GPIO_DDC1_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
158
case REG(DC_GPIO_DDC2_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
161
case REG(DC_GPIO_DDC3_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
164
case REG(DC_GPIO_DDC4_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
167
case REG(DC_GPIO_DDC5_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
170
case REG(DC_GPIO_DDCVGA_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
201
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
204
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
207
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
210
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
213
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
216
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
228
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
231
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
234
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
237
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
240
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
243
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
252
info->offset = REG(DC_GPIO_GENERIC_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
281
info->offset = REG(DC_GPIO_HPD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
73
case REG(DC_GPIO_GENERIC_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
122
case REG(DC_GPIO_GENLK_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
146
case REG(DC_GPIO_DDC1_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
149
case REG(DC_GPIO_DDC2_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
152
case REG(DC_GPIO_DDC3_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
155
case REG(DC_GPIO_DDC4_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
158
case REG(DC_GPIO_DDC5_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
161
case REG(DC_GPIO_DDCVGA_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
182
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
185
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
188
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
191
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
194
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
197
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
209
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
212
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
215
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
218
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
221
info->offset = REG(DC_GPIO_DDC5_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
224
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
233
info->offset = REG(DC_GPIO_GENERIC_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
259
info->offset = REG(DC_GPIO_HPD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
71
case REG(DC_GPIO_GENERIC_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
98
case REG(DC_GPIO_HPD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
122
case REG(DC_GPIO_DDC1_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
125
case REG(DC_GPIO_DDC2_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
128
case REG(DC_GPIO_DDC3_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
131
case REG(DC_GPIO_DDC4_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
134
case REG(DC_GPIO_DDCVGA_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
166
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
169
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
172
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
175
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
181
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
193
info->offset = REG(DC_GPIO_DDC1_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
196
info->offset = REG(DC_GPIO_DDC2_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
199
info->offset = REG(DC_GPIO_DDC3_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
202
info->offset = REG(DC_GPIO_DDC4_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
208
info->offset = REG(DC_GPIO_DDCVGA_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
217
info->offset = REG(DC_GPIO_GENERIC_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
243
info->offset = REG(DC_GPIO_HPD_A);
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
46
case REG(DC_GPIO_GENERIC_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
73
case REG(DC_GPIO_HPD_A):
drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
97
case REG(DC_GPIO_GENLK_A):
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
35
.type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
49
.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
53
.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
54
.phy_aux_cntl = REG(PHY_AUX_CNTL), \
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
55
.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
58
.type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
75
.type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
94
.phy_aux_cntl = REG(PHY_AUX_CNTL), \
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
95
.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h
32
.type ## _reg = REG(DC_GPIO_GENERIC_## type),\
drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h
46
.mux = REG(DC_GENERIC ## id),\
drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h
40
.type ## _reg = REG(DC_GPIO_HPD_## type),\
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
54
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
625
if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
64
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
74
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
84
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
436
if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
518
if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A))
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
520
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
529
if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B))
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
531
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
540
if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C))
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
542
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
551
if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D))
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
553
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
634
if (REG(DCN_VM_FAULT_ADDR_MSB))
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
637
if (REG(DCN_VM_FAULT_ADDR_LSB))
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
640
if (REG(DCN_VM_FAULT_CNTL))
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
643
if (REG(DCN_VM_FAULT_STATUS)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
649
if (REG(DCHUBBUB_TEST_DEBUG_INDEX) && REG(DCHUBBUB_TEST_DEBUG_DATA)) {
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
654
if (REG(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL))
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
657
if (REG(DCHUBBUB_ARB_DRAM_STATE_CNTL))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1001
if (REG(NOM_PARAMETERS_3))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
636
if (REG(NOM_PARAMETERS_0))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
640
if (REG(NOM_PARAMETERS_1))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
657
if (REG(NOM_PARAMETERS_2))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
661
if (REG(NOM_PARAMETERS_3))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
939
if (REG(PREFETCH_SETTINS))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
962
if (REG(NOM_PARAMETERS_0))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
966
if (REG(NOM_PARAMETERS_1))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
984
if (REG(PREFETCH_SETTINS_C))
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
997
if (REG(NOM_PARAMETERS_2))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
110
if (REG(NOM_PARAMETERS_0))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
114
if (REG(NOM_PARAMETERS_1))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1176
if (REG(PREFETCH_SETTINS))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1199
if (REG(NOM_PARAMETERS_0))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1203
if (REG(NOM_PARAMETERS_1))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1221
if (REG(PREFETCH_SETTINS_C))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1234
if (REG(NOM_PARAMETERS_2))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1238
if (REG(NOM_PARAMETERS_3))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
131
if (REG(NOM_PARAMETERS_2))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
135
if (REG(NOM_PARAMETERS_3))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1358
if (REG(DCHUBP_CNTL))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1361
if (REG(DCSURF_FLIP_CONTROL))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1511
if (REG(NOM_PARAMETERS_0))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1514
if (REG(NOM_PARAMETERS_1))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1529
if (REG(NOM_PARAMETERS_2))
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1532
if (REG(NOM_PARAMETERS_3))
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
393
if (REG(NOM_PARAMETERS_0))
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
396
if (REG(NOM_PARAMETERS_1))
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
411
if (REG(NOM_PARAMETERS_2))
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
414
if (REG(NOM_PARAMETERS_3))
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
468
if (REG(UCLK_PSTATE_FORCE))
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
471
if (REG(DCHUBP_CNTL))
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
474
if (REG(DCSURF_FLIP_CONTROL))
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
280
if (REG(NOM_PARAMETERS_0))
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
284
if (REG(NOM_PARAMETERS_1))
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
301
if (REG(NOM_PARAMETERS_2))
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
305
if (REG(NOM_PARAMETERS_3))
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
120
if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
140
if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
148
if (REG(DCFEV_CLOCK_CONTROL))
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
200
if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1017
if (REG(DC_IP_REQUEST_CNTL)) {
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1495
if (REG(DC_IP_REQUEST_CNTL)) {
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
258
if (REG(MPC_CRC_RESULT_GB))
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
261
if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
905
if (REG(DOMAIN1_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
966
if (REG(DOMAIN0_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1276
if (REG(DC_IP_REQUEST_CNTL)) {
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
327
if (REG(DOMAIN8_PG_CONFIG))
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
329
if (REG(DOMAIN10_PG_CONFIG))
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
337
if (REG(DOMAIN9_PG_CONFIG))
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
339
if (REG(DOMAIN11_PG_CONFIG))
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
346
if (REG(DOMAIN19_PG_CONFIG))
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
348
if (REG(DOMAIN20_PG_CONFIG))
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
350
if (REG(DOMAIN21_PG_CONFIG))
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
471
if (REG(DOMAIN16_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
546
if (REG(DOMAIN1_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
628
if (REG(DOMAIN0_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
109
if (REG(DOMAIN0_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
168
if (REG(DOMAIN16_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
52
if (REG(DOMAIN1_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
454
if (REG(DOMAIN0_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
563
if (REG(DOMAIN1_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
178
if (REG(DOMAIN0_PG_CONFIG) == 0)
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2959
if (REG(DC_IP_REQUEST_CNTL)) {
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2975
if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL))
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3053
if (REG(DC_IP_REQUEST_CNTL)) {
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3072
if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL))
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3521
if (REG(DC_IP_REQUEST_CNTL))
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3535
if (REG(DC_IP_REQUEST_CNTL))
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3547
if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.dpp_pg_control)
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3551
if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.hubp_pg_control)
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
157
generic_reg_get(CTX, REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
161
generic_reg_get2(CTX, REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
166
generic_reg_get3(CTX, REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
172
generic_reg_get4(CTX, REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
179
generic_reg_get5(CTX, REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
187
generic_reg_get6(CTX, REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
196
generic_reg_get7(CTX, REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
206
generic_reg_get8(CTX, REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
220
REG(reg_name), FN(reg_name, field), val,\
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
227
REG(reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
40
dm_read_reg(CTX, REG(reg_name))
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
43
dm_write_reg(CTX, REG(reg_name), value)
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
448
REG(index_reg_name), REG(data_reg_name), IND_REG(index), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
459
generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index))
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
462
generic_indirect_reg_get(CTX, REG(index_reg_name), REG(data_reg_name), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
472
REG(index_reg_name), REG(data_reg_name), IND_REG(index), \
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
56
REG(reg_name), \
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
372
if (REG(MUX[opp_id]))
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
391
if (opp_id < MAX_OPP && REG(MUX[opp_id]))
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
472
if (opp_id < MAX_OPP && REG(MUX[opp_id]))
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
170
ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
171
ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
173
ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
174
ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
229
ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
230
ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
232
ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
233
ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
330
gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
331
gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
332
gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
333
gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
334
gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
335
gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
336
gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
337
gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
338
gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
339
gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
340
gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
341
gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
342
gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
343
gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
357
gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
358
gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
359
gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
360
gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
361
gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
362
gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
363
gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
364
gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
365
gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
366
gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
367
gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
368
gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
369
gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
370
gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1101
gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1102
gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1111
gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1112
gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1176
gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1177
gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1186
gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1187
gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1330
ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1331
ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1333
ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1334
ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1373
ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1374
ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1376
ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1377
ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
243
gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
244
gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
245
gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
246
gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
247
gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
248
gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
249
gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
250
gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
251
gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
252
gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
253
gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
254
gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
255
gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
256
gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
258
gam_regs.offset_b = REG(MPCC_OGAM_RAMA_OFFSET_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
259
gam_regs.offset_g = REG(MPCC_OGAM_RAMA_OFFSET_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
260
gam_regs.offset_r = REG(MPCC_OGAM_RAMA_OFFSET_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
261
gam_regs.start_base_cntl_b = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
262
gam_regs.start_base_cntl_g = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
263
gam_regs.start_base_cntl_r = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
276
gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
277
gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
278
gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
279
gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
280
gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
281
gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
282
gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
283
gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
284
gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
285
gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
286
gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
287
gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
288
gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
289
gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
291
gam_regs.offset_b = REG(MPCC_OGAM_RAMB_OFFSET_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
292
gam_regs.offset_g = REG(MPCC_OGAM_RAMB_OFFSET_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
293
gam_regs.offset_r = REG(MPCC_OGAM_RAMB_OFFSET_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
294
gam_regs.start_base_cntl_b = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
295
gam_regs.start_base_cntl_g = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
296
gam_regs.start_base_cntl_r = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
55
if (REG(MUX[opp_id]))
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
71
if (mpcc_id < MAX_OPP && REG(MUX[mpcc_id]))
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
177
gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
178
gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
179
gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
180
gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
181
gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
182
gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
183
gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
184
gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
185
gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
186
gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
187
gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
188
gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
189
gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
190
gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
206
gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
207
gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
208
gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
209
gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
210
gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
211
gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
212
gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
213
gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
214
gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
215
gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
216
gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
217
gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
218
gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
219
gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
316
gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
317
gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
320
gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
321
gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
350
gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
351
gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
354
gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
355
gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
385
gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
386
gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
389
gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
390
gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
482
gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
483
gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
486
gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
487
gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
505
gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
506
gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
509
gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
510
gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
528
gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
529
gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
532
gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
533
gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[mpcc_id]);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
268
if (REG(OTG_INTERLACE_CONTROL)) {
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
308
if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
374
if (REG(OTG_INTERLACE_CONTROL)) {
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
204
if (REG(OPTC_MEMORY_CONFIG))
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
249
if (REG(OPTC_MEMORY_CONFIG))
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
67
if (REG(OPTC_MEMORY_CONFIG))
drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
112
dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
51
#define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
54
((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
59
dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
86
dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)
drivers/gpu/drm/bridge/tda998x_drv.c
113
#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
drivers/gpu/drm/bridge/tda998x_drv.c
114
#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
121
#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
drivers/gpu/drm/bridge/tda998x_drv.c
122
#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
125
#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
126
#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
127
#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
131
#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
135
#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
136
#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
137
#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
139
#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
140
#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
141
#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
142
#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
143
#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
144
#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
149
#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
154
#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
159
#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
168
#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
175
#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
178
#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
181
#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
182
#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
185
#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
186
#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
187
#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
188
#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
189
#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
190
#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
191
#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
192
#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
193
#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
194
#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
195
#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
196
#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
197
#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
198
#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
199
#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
200
#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
201
#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
202
#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
203
#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
204
#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
205
#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
206
#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
207
#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
208
#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
209
#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
210
#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
211
#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
212
#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
213
#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
214
#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
215
#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
216
#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
217
#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
218
#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
219
#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
220
#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
221
#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
222
#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
223
#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
224
#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
225
#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
226
#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
234
#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
242
#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
243
#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
248
#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
254
#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
256
#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
260
#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
drivers/gpu/drm/bridge/tda998x_drv.c
268
#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
272
#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
275
#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
279
#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
280
#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
281
#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
282
#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
283
#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
284
#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
285
#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
286
#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
287
#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
294
#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
298
#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
302
#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
drivers/gpu/drm/bridge/tda998x_drv.c
304
#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
305
#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
306
#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
307
#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
308
#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
312
#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
313
#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
314
#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
315
#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
316
#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
320
#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
326
#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
329
#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
330
#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
331
#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
332
#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
333
#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
334
#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
335
#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
336
#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
339
#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
343
#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
346
#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
352
#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
356
#define REG_TX3 REG(0x12, 0x9a) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
357
#define REG_TX4 REG(0x12, 0x9b) /* read/write */
drivers/gpu/drm/bridge/tda998x_drv.c
359
#define REG_TX33 REG(0x12, 0xb8) /* read/write */
drivers/gpu/drm/i915/gt/intel_lrc.c
112
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
113
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
114
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
115
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
116
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
117
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
118
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
119
REG(0x11c),
drivers/gpu/drm/i915/gt/intel_lrc.c
120
REG(0x114),
drivers/gpu/drm/i915/gt/intel_lrc.c
121
REG(0x118),
drivers/gpu/drm/i915/gt/intel_lrc.c
138
REG(0x028),
drivers/gpu/drm/i915/gt/intel_lrc.c
147
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
148
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
149
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
150
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
151
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
152
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
153
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
154
REG(0x11c),
drivers/gpu/drm/i915/gt/intel_lrc.c
155
REG(0x114),
drivers/gpu/drm/i915/gt/intel_lrc.c
156
REG(0x118),
drivers/gpu/drm/i915/gt/intel_lrc.c
157
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
158
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
159
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
179
REG(0x028),
drivers/gpu/drm/i915/gt/intel_lrc.c
180
REG(0x09c),
drivers/gpu/drm/i915/gt/intel_lrc.c
181
REG(0x0c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
182
REG(0x178),
drivers/gpu/drm/i915/gt/intel_lrc.c
183
REG(0x17c),
drivers/gpu/drm/i915/gt/intel_lrc.c
185
REG(0x170),
drivers/gpu/drm/i915/gt/intel_lrc.c
186
REG(0x150),
drivers/gpu/drm/i915/gt/intel_lrc.c
187
REG(0x154),
drivers/gpu/drm/i915/gt/intel_lrc.c
188
REG(0x158),
drivers/gpu/drm/i915/gt/intel_lrc.c
222
REG(0x068),
drivers/gpu/drm/i915/gt/intel_lrc.c
231
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
232
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
233
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
234
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
235
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
236
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
237
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
238
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
239
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
240
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
241
REG(0x180),
drivers/gpu/drm/i915/gt/intel_lrc.c
263
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
264
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
265
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
266
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
267
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
268
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
269
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
270
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
271
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
272
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
273
REG(0x180),
drivers/gpu/drm/i915/gt/intel_lrc.c
275
REG(0x120),
drivers/gpu/drm/i915/gt/intel_lrc.c
276
REG(0x124),
drivers/gpu/drm/i915/gt/intel_lrc.c
297
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
298
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
299
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
300
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
301
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
302
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
303
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
304
REG(0x11c),
drivers/gpu/drm/i915/gt/intel_lrc.c
305
REG(0x114),
drivers/gpu/drm/i915/gt/intel_lrc.c
306
REG(0x118),
drivers/gpu/drm/i915/gt/intel_lrc.c
307
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
308
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
309
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
325
REG(0x0c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
334
REG(0x34),
drivers/gpu/drm/i915/gt/intel_lrc.c
335
REG(0x30),
drivers/gpu/drm/i915/gt/intel_lrc.c
336
REG(0x38),
drivers/gpu/drm/i915/gt/intel_lrc.c
337
REG(0x3c),
drivers/gpu/drm/i915/gt/intel_lrc.c
338
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
339
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
340
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
341
REG(0x11c),
drivers/gpu/drm/i915/gt/intel_lrc.c
342
REG(0x114),
drivers/gpu/drm/i915/gt/intel_lrc.c
343
REG(0x118),
drivers/gpu/drm/i915/gt/intel_lrc.c
344
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
345
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
346
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
362
REG(0xc8),
drivers/gpu/drm/i915/gt/intel_lrc.c
366
REG(0x28),
drivers/gpu/drm/i915/gt/intel_lrc.c
367
REG(0x9c),
drivers/gpu/drm/i915/gt/intel_lrc.c
368
REG(0xc0),
drivers/gpu/drm/i915/gt/intel_lrc.c
369
REG(0x178),
drivers/gpu/drm/i915/gt/intel_lrc.c
370
REG(0x17c),
drivers/gpu/drm/i915/gt/intel_lrc.c
372
REG(0x170),
drivers/gpu/drm/i915/gt/intel_lrc.c
373
REG(0x150),
drivers/gpu/drm/i915/gt/intel_lrc.c
374
REG(0x154),
drivers/gpu/drm/i915/gt/intel_lrc.c
375
REG(0x158),
drivers/gpu/drm/i915/gt/intel_lrc.c
409
REG(0x68),
drivers/gpu/drm/i915/gt/intel_lrc.c
418
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
419
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
420
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
421
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
422
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
423
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
424
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
425
REG(0x11c),
drivers/gpu/drm/i915/gt/intel_lrc.c
426
REG(0x114),
drivers/gpu/drm/i915/gt/intel_lrc.c
427
REG(0x118),
drivers/gpu/drm/i915/gt/intel_lrc.c
428
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
429
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
430
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
431
REG(0x180),
drivers/gpu/drm/i915/gt/intel_lrc.c
446
REG(0x1b0),
drivers/gpu/drm/i915/gt/intel_lrc.c
450
REG(0x0c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
459
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
460
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
461
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
462
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
463
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
464
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
465
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
466
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
467
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
468
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
469
REG(0x180),
drivers/gpu/drm/i915/gt/intel_lrc.c
485
REG(0x1b0),
drivers/gpu/drm/i915/gt/intel_lrc.c
491
REG(0x0c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
501
REG(0x028),
drivers/gpu/drm/i915/gt/intel_lrc.c
502
REG(0x09c),
drivers/gpu/drm/i915/gt/intel_lrc.c
503
REG(0x0c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
504
REG(0x178),
drivers/gpu/drm/i915/gt/intel_lrc.c
505
REG(0x17c),
drivers/gpu/drm/i915/gt/intel_lrc.c
507
REG(0x170),
drivers/gpu/drm/i915/gt/intel_lrc.c
508
REG(0x150),
drivers/gpu/drm/i915/gt/intel_lrc.c
509
REG(0x154),
drivers/gpu/drm/i915/gt/intel_lrc.c
510
REG(0x158),
drivers/gpu/drm/i915/gt/intel_lrc.c
544
REG(0x068),
drivers/gpu/drm/i915/gt/intel_lrc.c
545
REG(0x084),
drivers/gpu/drm/i915/gt/intel_lrc.c
555
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
556
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
557
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
558
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
559
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
560
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
561
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
562
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
563
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
564
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
565
REG(0x180),
drivers/gpu/drm/i915/gt/intel_lrc.c
567
REG(0x120),
drivers/gpu/drm/i915/gt/intel_lrc.c
568
REG(0x124),
drivers/gpu/drm/i915/gt/intel_lrc.c
583
REG(0x1b0),
drivers/gpu/drm/i915/gt/intel_lrc.c
589
REG(0x0c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
598
REG(0x034),
drivers/gpu/drm/i915/gt/intel_lrc.c
599
REG(0x030),
drivers/gpu/drm/i915/gt/intel_lrc.c
600
REG(0x038),
drivers/gpu/drm/i915/gt/intel_lrc.c
601
REG(0x03c),
drivers/gpu/drm/i915/gt/intel_lrc.c
602
REG(0x168),
drivers/gpu/drm/i915/gt/intel_lrc.c
603
REG(0x140),
drivers/gpu/drm/i915/gt/intel_lrc.c
604
REG(0x110),
drivers/gpu/drm/i915/gt/intel_lrc.c
605
REG(0x1c0),
drivers/gpu/drm/i915/gt/intel_lrc.c
606
REG(0x1c4),
drivers/gpu/drm/i915/gt/intel_lrc.c
607
REG(0x1c8),
drivers/gpu/drm/i915/gt/intel_lrc.c
608
REG(0x180),
drivers/gpu/drm/i915/gt/intel_lrc.c
610
REG(0x120),
drivers/gpu/drm/i915/gt/intel_lrc.c
611
REG(0x124),
drivers/gpu/drm/i915/gt/intel_lrc.c
632
REG(0x0c8),
drivers/gpu/drm/panel/panel-novatek-nt39016.c
70
#define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 }
drivers/gpu/drm/tidss/tidss_dispc_regs.h
100
#define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
101
#define DISPC_CONNECTIONS REG(DISPC_CONNECTIONS)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
105
#define DISPC_MSS_VP1 REG(DISPC_MSS_VP1)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
106
#define DISPC_MSS_VP3 REG(DISPC_MSS_VP3)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
57
#define DSS_REVISION REG(DSS_REVISION)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
58
#define DSS_SYSCONFIG REG(DSS_SYSCONFIG)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
61
#define DSS_SYSSTATUS REG(DSS_SYSSTATUS)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
65
#define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
66
#define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
67
#define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
68
#define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
69
#define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
70
#define DISPC_VID_IRQENABLE(n) (REG(DISPC_VID_IRQENABLE) + (n) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
71
#define DISPC_VID_IRQSTATUS(n) (REG(DISPC_VID_IRQSTATUS) + (n) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
72
#define DISPC_VP_IRQENABLE(n) (REG(DISPC_VP_IRQENABLE) + (n) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
73
#define DISPC_VP_IRQSTATUS(n) (REG(DISPC_VP_IRQSTATUS) + (n) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
74
#define WB_IRQENABLE REG(WB_IRQENABLE)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
75
#define WB_IRQSTATUS REG(WB_IRQSTATUS)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
77
#define DISPC_GLOBAL_MFLAG_ATTRIBUTE REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
81
#define DISPC_GLOBAL_OUTPUT_ENABLE REG(DISPC_GLOBAL_OUTPUT_ENABLE)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
82
#define DISPC_GLOBAL_BUFFER REG(DISPC_GLOBAL_BUFFER)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
83
#define DSS_CBA_CFG REG(DSS_CBA_CFG)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
87
#define DISPC_DBG_CONTROL REG(DISPC_DBG_CONTROL)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
88
#define DISPC_DBG_STATUS REG(DISPC_DBG_STATUS)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
89
#define DISPC_CLKGATING_DISABLE REG(DISPC_CLKGATING_DISABLE)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
90
#define DISPC_SECURE_DISABLE REG(DISPC_SECURE_DISABLE)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
92
#define FBDC_REVISION_1 REG(FBDC_REVISION_1)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
93
#define FBDC_REVISION_2 REG(FBDC_REVISION_2)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
94
#define FBDC_REVISION_3 REG(FBDC_REVISION_3)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
95
#define FBDC_REVISION_4 REG(FBDC_REVISION_4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
96
#define FBDC_REVISION_5 REG(FBDC_REVISION_5)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
97
#define FBDC_REVISION_6 REG(FBDC_REVISION_6)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
98
#define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
99
#define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0)
drivers/gpu/drm/tilcdc/tilcdc_drv.c
415
REG(1, false, LCDC_PID_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
416
REG(1, true, LCDC_CTRL_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
417
REG(1, false, LCDC_STAT_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
418
REG(1, true, LCDC_RASTER_CTRL_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
419
REG(1, true, LCDC_RASTER_TIMING_0_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
420
REG(1, true, LCDC_RASTER_TIMING_1_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
421
REG(1, true, LCDC_RASTER_TIMING_2_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
422
REG(1, true, LCDC_DMA_CTRL_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
423
REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
424
REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
425
REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
426
REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
428
REG(2, false, LCDC_RAW_STAT_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
429
REG(2, false, LCDC_MASKED_STAT_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
430
REG(2, true, LCDC_INT_ENABLE_SET_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
431
REG(2, false, LCDC_INT_ENABLE_CLR_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
432
REG(2, false, LCDC_END_OF_INT_IND_REG),
drivers/gpu/drm/tilcdc/tilcdc_drv.c
433
REG(2, true, LCDC_CLK_ENABLE_REG),
drivers/gpu/drm/xe/xe_lrc.c
231
REG(0x034),
drivers/gpu/drm/xe/xe_lrc.c
232
REG(0x030),
drivers/gpu/drm/xe/xe_lrc.c
233
REG(0x038),
drivers/gpu/drm/xe/xe_lrc.c
234
REG(0x03c),
drivers/gpu/drm/xe/xe_lrc.c
235
REG(0x168),
drivers/gpu/drm/xe/xe_lrc.c
236
REG(0x140),
drivers/gpu/drm/xe/xe_lrc.c
237
REG(0x110),
drivers/gpu/drm/xe/xe_lrc.c
238
REG(0x1c0),
drivers/gpu/drm/xe/xe_lrc.c
239
REG(0x1c4),
drivers/gpu/drm/xe/xe_lrc.c
240
REG(0x1c8),
drivers/gpu/drm/xe/xe_lrc.c
241
REG(0x180),
drivers/gpu/drm/xe/xe_lrc.c
263
REG(0x034),
drivers/gpu/drm/xe/xe_lrc.c
264
REG(0x030),
drivers/gpu/drm/xe/xe_lrc.c
265
REG(0x038),
drivers/gpu/drm/xe/xe_lrc.c
266
REG(0x03c),
drivers/gpu/drm/xe/xe_lrc.c
267
REG(0x168),
drivers/gpu/drm/xe/xe_lrc.c
268
REG(0x140),
drivers/gpu/drm/xe/xe_lrc.c
269
REG(0x110),
drivers/gpu/drm/xe/xe_lrc.c
270
REG(0x1c0),
drivers/gpu/drm/xe/xe_lrc.c
271
REG(0x1c4),
drivers/gpu/drm/xe/xe_lrc.c
272
REG(0x1c8),
drivers/gpu/drm/xe/xe_lrc.c
273
REG(0x180),
drivers/gpu/drm/xe/xe_lrc.c
275
REG(0x120),
drivers/gpu/drm/xe/xe_lrc.c
276
REG(0x124),
drivers/gpu/drm/xe/xe_lrc.c
297
REG(0x034),
drivers/gpu/drm/xe/xe_lrc.c
298
REG(0x030),
drivers/gpu/drm/xe/xe_lrc.c
299
REG(0x038),
drivers/gpu/drm/xe/xe_lrc.c
300
REG(0x03c),
drivers/gpu/drm/xe/xe_lrc.c
301
REG(0x168),
drivers/gpu/drm/xe/xe_lrc.c
302
REG(0x140),
drivers/gpu/drm/xe/xe_lrc.c
303
REG(0x110),
drivers/gpu/drm/xe/xe_lrc.c
304
REG(0x1c0),
drivers/gpu/drm/xe/xe_lrc.c
305
REG(0x1c4),
drivers/gpu/drm/xe/xe_lrc.c
306
REG(0x1c8),
drivers/gpu/drm/xe/xe_lrc.c
307
REG(0x180),
drivers/gpu/drm/xe/xe_lrc.c
323
REG(0x1b0),
drivers/gpu/drm/xe/xe_lrc.c
329
REG(0x0c8),
drivers/gpu/drm/xe/xe_lrc.c
339
REG(0x028),
drivers/gpu/drm/xe/xe_lrc.c
340
REG(0x09c),
drivers/gpu/drm/xe/xe_lrc.c
341
REG(0x0c0),
drivers/gpu/drm/xe/xe_lrc.c
342
REG(0x178),
drivers/gpu/drm/xe/xe_lrc.c
343
REG(0x17c),
drivers/gpu/drm/xe/xe_lrc.c
345
REG(0x170),
drivers/gpu/drm/xe/xe_lrc.c
346
REG(0x150),
drivers/gpu/drm/xe/xe_lrc.c
347
REG(0x154),
drivers/gpu/drm/xe/xe_lrc.c
348
REG(0x158),
drivers/gpu/drm/xe/xe_lrc.c
382
REG(0x068),
drivers/gpu/drm/xe/xe_lrc.c
383
REG(0x084),
drivers/gpu/drm/xe/xe_lrc.c
393
REG(0x034),
drivers/gpu/drm/xe/xe_lrc.c
394
REG(0x030),
drivers/gpu/drm/xe/xe_lrc.c
395
REG(0x038),
drivers/gpu/drm/xe/xe_lrc.c
396
REG(0x03c),
drivers/gpu/drm/xe/xe_lrc.c
397
REG(0x168),
drivers/gpu/drm/xe/xe_lrc.c
398
REG(0x140),
drivers/gpu/drm/xe/xe_lrc.c
399
REG(0x110),
drivers/gpu/drm/xe/xe_lrc.c
400
REG(0x1c0),
drivers/gpu/drm/xe/xe_lrc.c
401
REG(0x1c4),
drivers/gpu/drm/xe/xe_lrc.c
402
REG(0x1c8),
drivers/gpu/drm/xe/xe_lrc.c
403
REG(0x180),
drivers/gpu/drm/xe/xe_lrc.c
419
REG(0x1b0),
drivers/gpu/drm/xe/xe_lrc.c
425
REG(0x0c8),
drivers/gpu/drm/xe/xe_lrc.c
434
REG(0x034),
drivers/gpu/drm/xe/xe_lrc.c
435
REG(0x030),
drivers/gpu/drm/xe/xe_lrc.c
436
REG(0x038),
drivers/gpu/drm/xe/xe_lrc.c
437
REG(0x03c),
drivers/gpu/drm/xe/xe_lrc.c
438
REG(0x168),
drivers/gpu/drm/xe/xe_lrc.c
439
REG(0x140),
drivers/gpu/drm/xe/xe_lrc.c
440
REG(0x110),
drivers/gpu/drm/xe/xe_lrc.c
441
REG(0x1c0),
drivers/gpu/drm/xe/xe_lrc.c
442
REG(0x1c4),
drivers/gpu/drm/xe/xe_lrc.c
443
REG(0x1c8),
drivers/gpu/drm/xe/xe_lrc.c
444
REG(0x180),
drivers/gpu/drm/xe/xe_lrc.c
446
REG(0x120),
drivers/gpu/drm/xe/xe_lrc.c
447
REG(0x124),
drivers/gpu/drm/xe/xe_lrc.c
462
REG(0x1b0),
drivers/gpu/drm/xe/xe_lrc.c
468
REG(0x0c8),
drivers/gpu/drm/xe/xe_lrc.c
477
REG(0x034),
drivers/gpu/drm/xe/xe_lrc.c
478
REG(0x030),
drivers/gpu/drm/xe/xe_lrc.c
479
REG(0x038),
drivers/gpu/drm/xe/xe_lrc.c
480
REG(0x03c),
drivers/gpu/drm/xe/xe_lrc.c
481
REG(0x168),
drivers/gpu/drm/xe/xe_lrc.c
482
REG(0x140),
drivers/gpu/drm/xe/xe_lrc.c
483
REG(0x110),
drivers/gpu/drm/xe/xe_lrc.c
484
REG(0x1c0),
drivers/gpu/drm/xe/xe_lrc.c
485
REG(0x1c4),
drivers/gpu/drm/xe/xe_lrc.c
486
REG(0x1c8),
drivers/gpu/drm/xe/xe_lrc.c
487
REG(0x180),
drivers/gpu/drm/xe/xe_lrc.c
489
REG(0x120),
drivers/gpu/drm/xe/xe_lrc.c
490
REG(0x124),
drivers/gpu/drm/xe/xe_lrc.c
511
REG(0x0c8),
drivers/gpu/drm/xe/xe_lrc.c
520
REG(0x034), /* [0x04] RING_BUFFER_HEAD */ \
drivers/gpu/drm/xe/xe_lrc.c
521
REG(0x030), /* [0x06] RING_BUFFER_TAIL */ \
drivers/gpu/drm/xe/xe_lrc.c
522
REG(0x038), /* [0x08] RING_BUFFER_START */ \
drivers/gpu/drm/xe/xe_lrc.c
523
REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */ \
drivers/gpu/drm/xe/xe_lrc.c
524
REG(0x168), /* [0x0c] BB_ADDR_UDW */ \
drivers/gpu/drm/xe/xe_lrc.c
525
REG(0x140), /* [0x0e] BB_ADDR */ \
drivers/gpu/drm/xe/xe_lrc.c
526
REG(0x110), /* [0x10] BB_STATE */ \
drivers/gpu/drm/xe/xe_lrc.c
527
REG(0x1c0), /* [0x12] BB_PER_CTX_PTR */ \
drivers/gpu/drm/xe/xe_lrc.c
528
REG(0x1c4), /* [0x14] RCS_INDIRECT_CTX */ \
drivers/gpu/drm/xe/xe_lrc.c
529
REG(0x1c8), /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \
drivers/gpu/drm/xe/xe_lrc.c
530
REG(0x180), /* [0x18] CCID */ \
drivers/gpu/drm/xe/xe_lrc.c
532
REG(0x120), /* [0x1c] PRT_BB_STATE */ \
drivers/gpu/drm/xe/xe_lrc.c
533
REG(0x124), /* [0x1e] PRT_BB_STATE_UDW */ \
drivers/gpu/drm/xe/xe_lrc.c
539
REG(0x108), /* [0x26] INDIRECT_RING_STATE */ \
drivers/gpu/drm/xe/xe_lrc.c
557
REG(0x0c8), /* [0x48] R_PWR_CLK_STATE */
drivers/gpu/drm/xe/xe_lrc.c
582
REG(0x034), /* [0x02] RING_BUFFER_HEAD */
drivers/gpu/drm/xe/xe_lrc.c
583
REG(0x030), /* [0x04] RING_BUFFER_TAIL */
drivers/gpu/drm/xe/xe_lrc.c
584
REG(0x038), /* [0x06] RING_BUFFER_START */
drivers/gpu/drm/xe/xe_lrc.c
585
REG(0x048), /* [0x08] RING_BUFFER_START_UDW */
drivers/gpu/drm/xe/xe_lrc.c
586
REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */
drivers/gpu/drm/xe/xe_lrc.c
590
REG(0x168), /* [0x12] BB_ADDR_UDW */
drivers/gpu/drm/xe/xe_lrc.c
591
REG(0x140), /* [0x14] BB_ADDR */
drivers/gpu/drm/xe/xe_lrc.c
592
REG(0x110), /* [0x16] BB_STATE */
drivers/hwmon/asb100.c
247
#define set_in_reg(REG, reg) \
drivers/hwmon/asb100.c
260
asb100_write_value(client, ASB100_REG_IN_##REG(nr), \
drivers/hwmon/asb100.c
429
#define set_temp_reg(REG, reg) \
drivers/hwmon/asb100.c
449
asb100_write_value(client, ASB100_REG_TEMP_##REG(nr+1), \
drivers/hwmon/smsc47b397.c
46
outb(reg, REG);
drivers/hwmon/smsc47b397.c
52
outb(reg, REG);
drivers/hwmon/smsc47b397.c
64
if (!request_muxed_region(REG, 2, DRVNAME))
drivers/hwmon/smsc47b397.c
67
outb(0x55, REG);
drivers/hwmon/smsc47b397.c
73
outb(0xAA, REG);
drivers/hwmon/smsc47b397.c
74
release_region(REG, 2);
drivers/hwmon/smsc47m1.c
49
outb(reg, REG);
drivers/hwmon/smsc47m1.c
56
outb(reg, REG);
drivers/hwmon/smsc47m1.c
66
if (!request_muxed_region(REG, 2, DRVNAME))
drivers/hwmon/smsc47m1.c
69
outb(0x55, REG);
drivers/hwmon/smsc47m1.c
76
outb(0xAA, REG);
drivers/hwmon/smsc47m1.c
77
release_region(REG, 2);
drivers/hwmon/w83627ehf.c
1022
w83627ehf_write_value(data, REG[nr], val); \
drivers/hwmon/w83627ehf.c
698
#define store_in_reg(REG, reg) \
drivers/hwmon/w83627ehf.c
707
w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
drivers/hwmon/w83627ehf.c
957
#define fan_functions(reg, REG) \
drivers/hwmon/w83627ehf.c
983
w83627ehf_write_value(data, REG[nr], val); \
drivers/hwmon/w83627ehf.c
993
#define fan_time_functions(reg, REG) \
drivers/hwmon/w83781d.c
259
#define store_in_reg(REG, reg) \
drivers/hwmon/w83781d.c
272
w83781d_write_value(data, W83781D_REG_IN_##REG(nr), \
drivers/hwmon/w83781d.c
364
#define store_temp_reg(REG, reg) \
drivers/hwmon/w83781d.c
379
w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
drivers/hwmon/w83781d.c
383
w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
drivers/hwmon/w83791d.c
369
#define store_in_reg(REG, reg) \
drivers/hwmon/w83791d.c
385
w83791d_write(client, W83791D_REG_IN_##REG[nr], data->in_##reg[nr]); \
drivers/hwmon/w83792d.c
364
#define store_in_reg(REG, reg) \
drivers/hwmon/w83792d.c
380
w83792d_write_value(client, W83792D_REG_IN_##REG[nr], \
drivers/hwmon/w83l786ng.c
245
#define store_in_reg(REG, reg) \
drivers/hwmon/w83l786ng.c
259
w83l786ng_write_value(client, W83L786NG_REG_IN_##REG(nr), \
drivers/iio/magnetometer/mmc35240.c
71
#define MMC35240_OTP_CONVERT_Y(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 6)
drivers/iio/magnetometer/mmc35240.c
74
#define MMC35240_OTP_CONVERT_Z(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 81)
drivers/irqchip/irq-realtek-rtl.c
111
pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
drivers/irqchip/irq-realtek-rtl.c
138
writel(0, REG(RTL_ICTL_GIMR));
drivers/irqchip/irq-realtek-rtl.c
140
write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0);
drivers/irqchip/irq-realtek-rtl.c
58
value = readl(REG(RTL_ICTL_GIMR));
drivers/irqchip/irq-realtek-rtl.c
60
writel(value, REG(RTL_ICTL_GIMR));
drivers/irqchip/irq-realtek-rtl.c
72
value = readl(REG(RTL_ICTL_GIMR));
drivers/irqchip/irq-realtek-rtl.c
74
writel(value, REG(RTL_ICTL_GIMR));
drivers/irqchip/irq-realtek-rtl.c
92
write_irr(REG(RTL_ICTL_IRR0), hw, 1);
drivers/media/dvb-frontends/stb0899_priv.h
243
#define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG))
drivers/media/tuners/tda18250.c
514
[REG] = { 0x22, 0x23, 0x24, 0x21, 0x0d, 0x0c, 0x0f, 0x14,
drivers/media/tuners/tda18250.c
586
ret = regmap_write_bits(dev->regmap, delsys_params[REG][i],
drivers/mmc/host/vub300.c
1860
u32 reg = REG(cmd);
drivers/net/dsa/ocelot/felix_vsc9959.c
100
REG(ANA_SG_GCL_TI_CONFIG, 0x007f90),
drivers/net/dsa/ocelot/felix_vsc9959.c
101
REG(ANA_SG_STATUS_REG_1, 0x008980),
drivers/net/dsa/ocelot/felix_vsc9959.c
102
REG(ANA_SG_STATUS_REG_2, 0x008984),
drivers/net/dsa/ocelot/felix_vsc9959.c
103
REG(ANA_SG_STATUS_REG_3, 0x008988),
drivers/net/dsa/ocelot/felix_vsc9959.c
104
REG(ANA_PORT_VLAN_CFG, 0x007800),
drivers/net/dsa/ocelot/felix_vsc9959.c
105
REG(ANA_PORT_DROP_CFG, 0x007804),
drivers/net/dsa/ocelot/felix_vsc9959.c
106
REG(ANA_PORT_QOS_CFG, 0x007808),
drivers/net/dsa/ocelot/felix_vsc9959.c
107
REG(ANA_PORT_VCAP_CFG, 0x00780c),
drivers/net/dsa/ocelot/felix_vsc9959.c
108
REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810),
drivers/net/dsa/ocelot/felix_vsc9959.c
109
REG(ANA_PORT_VCAP_S2_CFG, 0x00781c),
drivers/net/dsa/ocelot/felix_vsc9959.c
110
REG(ANA_PORT_PCP_DEI_MAP, 0x007820),
drivers/net/dsa/ocelot/felix_vsc9959.c
111
REG(ANA_PORT_CPU_FWD_CFG, 0x007860),
drivers/net/dsa/ocelot/felix_vsc9959.c
112
REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864),
drivers/net/dsa/ocelot/felix_vsc9959.c
113
REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868),
drivers/net/dsa/ocelot/felix_vsc9959.c
114
REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c),
drivers/net/dsa/ocelot/felix_vsc9959.c
115
REG(ANA_PORT_PORT_CFG, 0x007870),
drivers/net/dsa/ocelot/felix_vsc9959.c
116
REG(ANA_PORT_POL_CFG, 0x007874),
drivers/net/dsa/ocelot/felix_vsc9959.c
117
REG(ANA_PORT_PTP_CFG, 0x007878),
drivers/net/dsa/ocelot/felix_vsc9959.c
118
REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c),
drivers/net/dsa/ocelot/felix_vsc9959.c
119
REG(ANA_PORT_PTP_DLY2_CFG, 0x007880),
drivers/net/dsa/ocelot/felix_vsc9959.c
120
REG(ANA_PORT_SFID_CFG, 0x007884),
drivers/net/dsa/ocelot/felix_vsc9959.c
121
REG(ANA_PFC_PFC_CFG, 0x008800),
drivers/net/dsa/ocelot/felix_vsc9959.c
127
REG(ANA_AGGR_CFG, 0x008a68),
drivers/net/dsa/ocelot/felix_vsc9959.c
128
REG(ANA_CPUQ_CFG, 0x008a6c),
drivers/net/dsa/ocelot/felix_vsc9959.c
130
REG(ANA_CPUQ_8021_CFG, 0x008a74),
drivers/net/dsa/ocelot/felix_vsc9959.c
131
REG(ANA_DSCP_CFG, 0x008ab4),
drivers/net/dsa/ocelot/felix_vsc9959.c
132
REG(ANA_DSCP_REWR_CFG, 0x008bb4),
drivers/net/dsa/ocelot/felix_vsc9959.c
133
REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4),
drivers/net/dsa/ocelot/felix_vsc9959.c
134
REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14),
drivers/net/dsa/ocelot/felix_vsc9959.c
138
REG(ANA_DISCARD_CFG, 0x008c40),
drivers/net/dsa/ocelot/felix_vsc9959.c
139
REG(ANA_FID_CFG, 0x008c44),
drivers/net/dsa/ocelot/felix_vsc9959.c
140
REG(ANA_POL_PIR_CFG, 0x004000),
drivers/net/dsa/ocelot/felix_vsc9959.c
141
REG(ANA_POL_CIR_CFG, 0x004004),
drivers/net/dsa/ocelot/felix_vsc9959.c
142
REG(ANA_POL_MODE_CFG, 0x004008),
drivers/net/dsa/ocelot/felix_vsc9959.c
143
REG(ANA_POL_PIR_STATE, 0x00400c),
drivers/net/dsa/ocelot/felix_vsc9959.c
144
REG(ANA_POL_CIR_STATE, 0x004010),
drivers/net/dsa/ocelot/felix_vsc9959.c
146
REG(ANA_POL_FLOWC, 0x008c48),
drivers/net/dsa/ocelot/felix_vsc9959.c
147
REG(ANA_POL_HYST, 0x008cb4),
drivers/net/dsa/ocelot/felix_vsc9959.c
152
REG(QS_XTR_GRP_CFG, 0x000000),
drivers/net/dsa/ocelot/felix_vsc9959.c
153
REG(QS_XTR_RD, 0x000008),
drivers/net/dsa/ocelot/felix_vsc9959.c
154
REG(QS_XTR_FRM_PRUNING, 0x000010),
drivers/net/dsa/ocelot/felix_vsc9959.c
155
REG(QS_XTR_FLUSH, 0x000018),
drivers/net/dsa/ocelot/felix_vsc9959.c
156
REG(QS_XTR_DATA_PRESENT, 0x00001c),
drivers/net/dsa/ocelot/felix_vsc9959.c
157
REG(QS_XTR_CFG, 0x000020),
drivers/net/dsa/ocelot/felix_vsc9959.c
158
REG(QS_INJ_GRP_CFG, 0x000024),
drivers/net/dsa/ocelot/felix_vsc9959.c
159
REG(QS_INJ_WR, 0x00002c),
drivers/net/dsa/ocelot/felix_vsc9959.c
160
REG(QS_INJ_CTRL, 0x000034),
drivers/net/dsa/ocelot/felix_vsc9959.c
161
REG(QS_INJ_STATUS, 0x00003c),
drivers/net/dsa/ocelot/felix_vsc9959.c
162
REG(QS_INJ_ERR, 0x000040),
drivers/net/dsa/ocelot/felix_vsc9959.c
168
REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
drivers/net/dsa/ocelot/felix_vsc9959.c
169
REG(VCAP_CORE_MV_CFG, 0x000004),
drivers/net/dsa/ocelot/felix_vsc9959.c
171
REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
drivers/net/dsa/ocelot/felix_vsc9959.c
172
REG(VCAP_CACHE_MASK_DAT, 0x000108),
drivers/net/dsa/ocelot/felix_vsc9959.c
173
REG(VCAP_CACHE_ACTION_DAT, 0x000208),
drivers/net/dsa/ocelot/felix_vsc9959.c
174
REG(VCAP_CACHE_CNT_DAT, 0x000308),
drivers/net/dsa/ocelot/felix_vsc9959.c
175
REG(VCAP_CACHE_TG_DAT, 0x000388),
drivers/net/dsa/ocelot/felix_vsc9959.c
177
REG(VCAP_CONST_VCAP_VER, 0x000398),
drivers/net/dsa/ocelot/felix_vsc9959.c
178
REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
drivers/net/dsa/ocelot/felix_vsc9959.c
179
REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
drivers/net/dsa/ocelot/felix_vsc9959.c
180
REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
drivers/net/dsa/ocelot/felix_vsc9959.c
181
REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
drivers/net/dsa/ocelot/felix_vsc9959.c
182
REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
drivers/net/dsa/ocelot/felix_vsc9959.c
183
REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
drivers/net/dsa/ocelot/felix_vsc9959.c
184
REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
drivers/net/dsa/ocelot/felix_vsc9959.c
185
REG(VCAP_CONST_CORE_CNT, 0x0003b8),
drivers/net/dsa/ocelot/felix_vsc9959.c
186
REG(VCAP_CONST_IF_CNT, 0x0003bc),
drivers/net/dsa/ocelot/felix_vsc9959.c
190
REG(QSYS_PORT_MODE, 0x00f460),
drivers/net/dsa/ocelot/felix_vsc9959.c
191
REG(QSYS_SWITCH_PORT_MODE, 0x00f480),
drivers/net/dsa/ocelot/felix_vsc9959.c
192
REG(QSYS_STAT_CNT_CFG, 0x00f49c),
drivers/net/dsa/ocelot/felix_vsc9959.c
193
REG(QSYS_EEE_CFG, 0x00f4a0),
drivers/net/dsa/ocelot/felix_vsc9959.c
194
REG(QSYS_EEE_THRES, 0x00f4b8),
drivers/net/dsa/ocelot/felix_vsc9959.c
195
REG(QSYS_IGR_NO_SHARING, 0x00f4bc),
drivers/net/dsa/ocelot/felix_vsc9959.c
196
REG(QSYS_EGR_NO_SHARING, 0x00f4c0),
drivers/net/dsa/ocelot/felix_vsc9959.c
197
REG(QSYS_SW_STATUS, 0x00f4c4),
drivers/net/dsa/ocelot/felix_vsc9959.c
198
REG(QSYS_EXT_CPU_CFG, 0x00f4e0),
drivers/net/dsa/ocelot/felix_vsc9959.c
200
REG(QSYS_CPU_GROUP_MAP, 0x00f4e8),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_TFRM_MISC, 0x00f50c),
drivers/net/dsa/ocelot/felix_vsc9959.c
205
REG(QSYS_TFRM_PORT_DLY, 0x00f510),
drivers/net/dsa/ocelot/felix_vsc9959.c
206
REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514),
drivers/net/dsa/ocelot/felix_vsc9959.c
207
REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518),
drivers/net/dsa/ocelot/felix_vsc9959.c
208
REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520),
drivers/net/dsa/ocelot/felix_vsc9959.c
210
REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524),
drivers/net/dsa/ocelot/felix_vsc9959.c
211
REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528),
drivers/net/dsa/ocelot/felix_vsc9959.c
212
REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c),
drivers/net/dsa/ocelot/felix_vsc9959.c
213
REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530),
drivers/net/dsa/ocelot/felix_vsc9959.c
214
REG(QSYS_RED_PROFILE, 0x00f534),
drivers/net/dsa/ocelot/felix_vsc9959.c
215
REG(QSYS_RES_QOS_MODE, 0x00f574),
drivers/net/dsa/ocelot/felix_vsc9959.c
216
REG(QSYS_RES_CFG, 0x00c000),
drivers/net/dsa/ocelot/felix_vsc9959.c
217
REG(QSYS_RES_STAT, 0x00c004),
drivers/net/dsa/ocelot/felix_vsc9959.c
218
REG(QSYS_EGR_DROP_MODE, 0x00f578),
drivers/net/dsa/ocelot/felix_vsc9959.c
219
REG(QSYS_EQ_CTRL, 0x00f57c),
drivers/net/dsa/ocelot/felix_vsc9959.c
221
REG(QSYS_QMAXSDU_CFG_0, 0x00f584),
drivers/net/dsa/ocelot/felix_vsc9959.c
222
REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0),
drivers/net/dsa/ocelot/felix_vsc9959.c
223
REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc),
drivers/net/dsa/ocelot/felix_vsc9959.c
224
REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8),
drivers/net/dsa/ocelot/felix_vsc9959.c
225
REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4),
drivers/net/dsa/ocelot/felix_vsc9959.c
226
REG(QSYS_QMAXSDU_CFG_5, 0x00f610),
drivers/net/dsa/ocelot/felix_vsc9959.c
227
REG(QSYS_QMAXSDU_CFG_6, 0x00f62c),
drivers/net/dsa/ocelot/felix_vsc9959.c
228
REG(QSYS_QMAXSDU_CFG_7, 0x00f648),
drivers/net/dsa/ocelot/felix_vsc9959.c
229
REG(QSYS_PREEMPTION_CFG, 0x00f664),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_CIR_CFG, 0x000000),
drivers/net/dsa/ocelot/felix_vsc9959.c
231
REG(QSYS_EIR_CFG, 0x000004),
drivers/net/dsa/ocelot/felix_vsc9959.c
232
REG(QSYS_SE_CFG, 0x000008),
drivers/net/dsa/ocelot/felix_vsc9959.c
233
REG(QSYS_SE_DWRR_CFG, 0x00000c),
drivers/net/dsa/ocelot/felix_vsc9959.c
235
REG(QSYS_SE_DLB_SENSE, 0x000040),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_CIR_STATE, 0x000044),
drivers/net/dsa/ocelot/felix_vsc9959.c
237
REG(QSYS_EIR_STATE, 0x000048),
drivers/net/dsa/ocelot/felix_vsc9959.c
239
REG(QSYS_HSCH_MISC_CFG, 0x00f67c),
drivers/net/dsa/ocelot/felix_vsc9959.c
240
REG(QSYS_TAG_CONFIG, 0x00f680),
drivers/net/dsa/ocelot/felix_vsc9959.c
241
REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698),
drivers/net/dsa/ocelot/felix_vsc9959.c
242
REG(QSYS_PORT_MAX_SDU, 0x00f69c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_CFG_REG_1, 0x00f440),
drivers/net/dsa/ocelot/felix_vsc9959.c
244
REG(QSYS_PARAM_CFG_REG_2, 0x00f444),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_CFG_REG_3, 0x00f448),
drivers/net/dsa/ocelot/felix_vsc9959.c
246
REG(QSYS_PARAM_CFG_REG_4, 0x00f44c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_CFG_REG_5, 0x00f450),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_GCL_CFG_REG_1, 0x00f454),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_GCL_CFG_REG_2, 0x00f458),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_STATUS_REG_1, 0x00f400),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_STATUS_REG_2, 0x00f404),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_STATUS_REG_3, 0x00f408),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_STATUS_REG_5, 0x00f410),
drivers/net/dsa/ocelot/felix_vsc9959.c
255
REG(QSYS_PARAM_STATUS_REG_6, 0x00f414),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_STATUS_REG_7, 0x00f418),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_PARAM_STATUS_REG_9, 0x00f420),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(QSYS_GCL_STATUS_REG_1, 0x00f424),
drivers/net/dsa/ocelot/felix_vsc9959.c
260
REG(QSYS_GCL_STATUS_REG_2, 0x00f428),
drivers/net/dsa/ocelot/felix_vsc9959.c
264
REG(REW_PORT_VLAN_CFG, 0x000000),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(REW_TAG_CFG, 0x000004),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(REW_PORT_CFG, 0x000008),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(REW_DSCP_CFG, 0x00000c),
drivers/net/dsa/ocelot/felix_vsc9959.c
268
REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
drivers/net/dsa/ocelot/felix_vsc9959.c
269
REG(REW_PTP_CFG, 0x000050),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(REW_PTP_DLY1_CFG, 0x000054),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(REW_RED_TAG_CFG, 0x000058),
drivers/net/dsa/ocelot/felix_vsc9959.c
272
REG(REW_DSCP_REMAP_DP1_CFG, 0x000410),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(REW_DSCP_REMAP_CFG, 0x000510),
drivers/net/dsa/ocelot/felix_vsc9959.c
280
REG(SYS_COUNT_RX_OCTETS, 0x000000),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_UNICAST, 0x000004),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_MULTICAST, 0x000008),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_SHORTS, 0x000010),
drivers/net/dsa/ocelot/felix_vsc9959.c
285
REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_JABBERS, 0x000018),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_64, 0x000024),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_65_127, 0x000028),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_128_255, 0x00002c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_256_511, 0x000030),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_512_1023, 0x000034),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_1024_1526, 0x000038),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_1527_MAX, 0x00003c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PAUSE, 0x000040),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_CONTROL, 0x000044),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_LONGS, 0x000048),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_ASSEMBLY_ERRS, 0x0000b0),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_SMD_ERRS, 0x0000b4),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_ASSEMBLY_OK, 0x0000b8),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_MERGE_FRAGMENTS, 0x0000bc),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_OCTETS, 0x0000c0),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_UNICAST, 0x0000c4),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_MULTICAST, 0x0000c8),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_BROADCAST, 0x0000cc),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_SHORTS, 0x0000d0),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_FRAGMENTS, 0x0000d4),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_JABBERS, 0x0000d8),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 0x0000dc),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_SYM_ERRS, 0x0000e0),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_64, 0x0000e4),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_65_127, 0x0000e8),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_128_255, 0x0000ec),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_256_511, 0x0000f0),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_512_1023, 0x0000f4),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_1024_1526, 0x0000f8),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_1527_MAX, 0x0000fc),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_PAUSE, 0x000100),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_CONTROL, 0x000104),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_RX_PMAC_LONGS, 0x000108),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_OCTETS, 0x000200),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_UNICAST, 0x000204),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_MULTICAST, 0x000208),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_BROADCAST, 0x00020c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_COLLISION, 0x000210),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_DROPS, 0x000214),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_PAUSE, 0x000218),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_64, 0x00021c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_65_127, 0x000220),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_128_255, 0x000224),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_256_511, 0x000228),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_512_1023, 0x00022c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_1024_1526, 0x000230),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_1527_MAX, 0x000234),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_AGED, 0x000278),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_MM_HOLD, 0x00027c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_MERGE_FRAGMENTS, 0x000280),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_PMAC_OCTETS, 0x000284),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_PMAC_UNICAST, 0x000288),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_PMAC_MULTICAST, 0x00028c),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_PMAC_BROADCAST, 0x000290),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_PMAC_PAUSE, 0x000294),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_PMAC_64, 0x000298),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(SYS_COUNT_TX_PMAC_65_127, 0x00029c),
drivers/net/dsa/ocelot/felix_vsc9959.c
387
REG(SYS_COUNT_TX_PMAC_128_255, 0x0002a0),
drivers/net/dsa/ocelot/felix_vsc9959.c
388
REG(SYS_COUNT_TX_PMAC_256_511, 0x0002a4),
drivers/net/dsa/ocelot/felix_vsc9959.c
389
REG(SYS_COUNT_TX_PMAC_512_1023, 0x0002a8),
drivers/net/dsa/ocelot/felix_vsc9959.c
390
REG(SYS_COUNT_TX_PMAC_1024_1526, 0x0002ac),
drivers/net/dsa/ocelot/felix_vsc9959.c
391
REG(SYS_COUNT_TX_PMAC_1527_MAX, 0x0002b0),
drivers/net/dsa/ocelot/felix_vsc9959.c
392
REG(SYS_COUNT_DROP_LOCAL, 0x000400),
drivers/net/dsa/ocelot/felix_vsc9959.c
393
REG(SYS_COUNT_DROP_TAIL, 0x000404),
drivers/net/dsa/ocelot/felix_vsc9959.c
394
REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408),
drivers/net/dsa/ocelot/felix_vsc9959.c
395
REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c),
drivers/net/dsa/ocelot/felix_vsc9959.c
396
REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410),
drivers/net/dsa/ocelot/felix_vsc9959.c
397
REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414),
drivers/net/dsa/ocelot/felix_vsc9959.c
398
REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418),
drivers/net/dsa/ocelot/felix_vsc9959.c
399
REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c),
drivers/net/dsa/ocelot/felix_vsc9959.c
400
REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420),
drivers/net/dsa/ocelot/felix_vsc9959.c
401
REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424),
drivers/net/dsa/ocelot/felix_vsc9959.c
402
REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428),
drivers/net/dsa/ocelot/felix_vsc9959.c
403
REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c),
drivers/net/dsa/ocelot/felix_vsc9959.c
404
REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430),
drivers/net/dsa/ocelot/felix_vsc9959.c
405
REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434),
drivers/net/dsa/ocelot/felix_vsc9959.c
406
REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438),
drivers/net/dsa/ocelot/felix_vsc9959.c
407
REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c),
drivers/net/dsa/ocelot/felix_vsc9959.c
408
REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440),
drivers/net/dsa/ocelot/felix_vsc9959.c
409
REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444),
drivers/net/dsa/ocelot/felix_vsc9959.c
410
REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800),
drivers/net/dsa/ocelot/felix_vsc9959.c
411
REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804),
drivers/net/dsa/ocelot/felix_vsc9959.c
412
REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808),
drivers/net/dsa/ocelot/felix_vsc9959.c
413
REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c),
drivers/net/dsa/ocelot/felix_vsc9959.c
414
REG(SYS_RESET_CFG, 0x000e00),
drivers/net/dsa/ocelot/felix_vsc9959.c
415
REG(SYS_SR_ETYPE_CFG, 0x000e04),
drivers/net/dsa/ocelot/felix_vsc9959.c
416
REG(SYS_VLAN_ETYPE_CFG, 0x000e08),
drivers/net/dsa/ocelot/felix_vsc9959.c
417
REG(SYS_PORT_MODE, 0x000e0c),
drivers/net/dsa/ocelot/felix_vsc9959.c
418
REG(SYS_FRONT_PORT_MODE, 0x000e2c),
drivers/net/dsa/ocelot/felix_vsc9959.c
419
REG(SYS_FRM_AGING, 0x000e44),
drivers/net/dsa/ocelot/felix_vsc9959.c
420
REG(SYS_STAT_CFG, 0x000e48),
drivers/net/dsa/ocelot/felix_vsc9959.c
421
REG(SYS_SW_STATUS, 0x000e4c),
drivers/net/dsa/ocelot/felix_vsc9959.c
423
REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c),
drivers/net/dsa/ocelot/felix_vsc9959.c
424
REG(SYS_REW_MAC_LOW_CFG, 0x000e84),
drivers/net/dsa/ocelot/felix_vsc9959.c
425
REG(SYS_TIMESTAMP_OFFSET, 0x000e9c),
drivers/net/dsa/ocelot/felix_vsc9959.c
426
REG(SYS_PAUSE_CFG, 0x000ea0),
drivers/net/dsa/ocelot/felix_vsc9959.c
427
REG(SYS_PAUSE_TOT_CFG, 0x000ebc),
drivers/net/dsa/ocelot/felix_vsc9959.c
428
REG(SYS_ATOP, 0x000ec0),
drivers/net/dsa/ocelot/felix_vsc9959.c
429
REG(SYS_ATOP_TOT_CFG, 0x000edc),
drivers/net/dsa/ocelot/felix_vsc9959.c
430
REG(SYS_MAC_FC_CFG, 0x000ee0),
drivers/net/dsa/ocelot/felix_vsc9959.c
431
REG(SYS_MMGT, 0x000ef8),
drivers/net/dsa/ocelot/felix_vsc9959.c
435
REG(SYS_PTP_STATUS, 0x000f14),
drivers/net/dsa/ocelot/felix_vsc9959.c
436
REG(SYS_PTP_TXSTAMP, 0x000f18),
drivers/net/dsa/ocelot/felix_vsc9959.c
437
REG(SYS_PTP_NXT, 0x000f1c),
drivers/net/dsa/ocelot/felix_vsc9959.c
438
REG(SYS_PTP_CFG, 0x000f20),
drivers/net/dsa/ocelot/felix_vsc9959.c
439
REG(SYS_RAM_INIT, 0x000f24),
drivers/net/dsa/ocelot/felix_vsc9959.c
448
REG(PTP_PIN_CFG, 0x000000),
drivers/net/dsa/ocelot/felix_vsc9959.c
449
REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
drivers/net/dsa/ocelot/felix_vsc9959.c
450
REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
drivers/net/dsa/ocelot/felix_vsc9959.c
451
REG(PTP_PIN_TOD_NSEC, 0x00000c),
drivers/net/dsa/ocelot/felix_vsc9959.c
452
REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
drivers/net/dsa/ocelot/felix_vsc9959.c
453
REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
drivers/net/dsa/ocelot/felix_vsc9959.c
454
REG(PTP_CFG_MISC, 0x0000a0),
drivers/net/dsa/ocelot/felix_vsc9959.c
455
REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
drivers/net/dsa/ocelot/felix_vsc9959.c
456
REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
drivers/net/dsa/ocelot/felix_vsc9959.c
460
REG(GCB_SOFT_RST, 0x000004),
drivers/net/dsa/ocelot/felix_vsc9959.c
464
REG(DEV_CLOCK_CFG, 0x0),
drivers/net/dsa/ocelot/felix_vsc9959.c
465
REG(DEV_PORT_MISC, 0x4),
drivers/net/dsa/ocelot/felix_vsc9959.c
466
REG(DEV_EVENTS, 0x8),
drivers/net/dsa/ocelot/felix_vsc9959.c
467
REG(DEV_EEE_CFG, 0xc),
drivers/net/dsa/ocelot/felix_vsc9959.c
468
REG(DEV_RX_PATH_DELAY, 0x10),
drivers/net/dsa/ocelot/felix_vsc9959.c
469
REG(DEV_TX_PATH_DELAY, 0x14),
drivers/net/dsa/ocelot/felix_vsc9959.c
470
REG(DEV_PTP_PREDICT_CFG, 0x18),
drivers/net/dsa/ocelot/felix_vsc9959.c
471
REG(DEV_MAC_ENA_CFG, 0x1c),
drivers/net/dsa/ocelot/felix_vsc9959.c
472
REG(DEV_MAC_MODE_CFG, 0x20),
drivers/net/dsa/ocelot/felix_vsc9959.c
473
REG(DEV_MAC_MAXLEN_CFG, 0x24),
drivers/net/dsa/ocelot/felix_vsc9959.c
474
REG(DEV_MAC_TAGS_CFG, 0x28),
drivers/net/dsa/ocelot/felix_vsc9959.c
475
REG(DEV_MAC_ADV_CHK_CFG, 0x2c),
drivers/net/dsa/ocelot/felix_vsc9959.c
476
REG(DEV_MAC_IFG_CFG, 0x30),
drivers/net/dsa/ocelot/felix_vsc9959.c
477
REG(DEV_MAC_HDX_CFG, 0x34),
drivers/net/dsa/ocelot/felix_vsc9959.c
478
REG(DEV_MAC_DBG_CFG, 0x38),
drivers/net/dsa/ocelot/felix_vsc9959.c
479
REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c),
drivers/net/dsa/ocelot/felix_vsc9959.c
480
REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40),
drivers/net/dsa/ocelot/felix_vsc9959.c
481
REG(DEV_MAC_STICKY, 0x44),
drivers/net/dsa/ocelot/felix_vsc9959.c
482
REG(DEV_MM_ENABLE_CONFIG, 0x48),
drivers/net/dsa/ocelot/felix_vsc9959.c
483
REG(DEV_MM_VERIF_CONFIG, 0x4C),
drivers/net/dsa/ocelot/felix_vsc9959.c
484
REG(DEV_MM_STATUS, 0x50),
drivers/net/dsa/ocelot/felix_vsc9959.c
50
REG(ANA_ADVLEARN, 0x0089a0),
drivers/net/dsa/ocelot/felix_vsc9959.c
51
REG(ANA_VLANMASK, 0x0089a4),
drivers/net/dsa/ocelot/felix_vsc9959.c
53
REG(ANA_ANAGEFIL, 0x0089ac),
drivers/net/dsa/ocelot/felix_vsc9959.c
54
REG(ANA_ANEVENTS, 0x0089b0),
drivers/net/dsa/ocelot/felix_vsc9959.c
55
REG(ANA_STORMLIMIT_BURST, 0x0089b4),
drivers/net/dsa/ocelot/felix_vsc9959.c
56
REG(ANA_STORMLIMIT_CFG, 0x0089b8),
drivers/net/dsa/ocelot/felix_vsc9959.c
57
REG(ANA_ISOLATED_PORTS, 0x0089c8),
drivers/net/dsa/ocelot/felix_vsc9959.c
58
REG(ANA_COMMUNITY_PORTS, 0x0089cc),
drivers/net/dsa/ocelot/felix_vsc9959.c
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REG(ANA_AUTOAGE, 0x0089d0),
drivers/net/dsa/ocelot/felix_vsc9959.c
60
REG(ANA_MACTOPTIONS, 0x0089d4),
drivers/net/dsa/ocelot/felix_vsc9959.c
61
REG(ANA_LEARNDISC, 0x0089d8),
drivers/net/dsa/ocelot/felix_vsc9959.c
62
REG(ANA_AGENCTRL, 0x0089dc),
drivers/net/dsa/ocelot/felix_vsc9959.c
63
REG(ANA_MIRRORPORTS, 0x0089e0),
drivers/net/dsa/ocelot/felix_vsc9959.c
64
REG(ANA_EMIRRORPORTS, 0x0089e4),
drivers/net/dsa/ocelot/felix_vsc9959.c
65
REG(ANA_FLOODING, 0x0089e8),
drivers/net/dsa/ocelot/felix_vsc9959.c
66
REG(ANA_FLOODING_IPMC, 0x008a08),
drivers/net/dsa/ocelot/felix_vsc9959.c
67
REG(ANA_SFLOW_CFG, 0x008a0c),
drivers/net/dsa/ocelot/felix_vsc9959.c
68
REG(ANA_PORT_MODE, 0x008a28),
drivers/net/dsa/ocelot/felix_vsc9959.c
69
REG(ANA_CUT_THRU_CFG, 0x008a48),
drivers/net/dsa/ocelot/felix_vsc9959.c
70
REG(ANA_PGID_PGID, 0x008400),
drivers/net/dsa/ocelot/felix_vsc9959.c
71
REG(ANA_TABLES_ANMOVED, 0x007f1c),
drivers/net/dsa/ocelot/felix_vsc9959.c
72
REG(ANA_TABLES_MACHDATA, 0x007f20),
drivers/net/dsa/ocelot/felix_vsc9959.c
73
REG(ANA_TABLES_MACLDATA, 0x007f24),
drivers/net/dsa/ocelot/felix_vsc9959.c
74
REG(ANA_TABLES_STREAMDATA, 0x007f28),
drivers/net/dsa/ocelot/felix_vsc9959.c
75
REG(ANA_TABLES_MACACCESS, 0x007f2c),
drivers/net/dsa/ocelot/felix_vsc9959.c
76
REG(ANA_TABLES_MACTINDX, 0x007f30),
drivers/net/dsa/ocelot/felix_vsc9959.c
77
REG(ANA_TABLES_VLANACCESS, 0x007f34),
drivers/net/dsa/ocelot/felix_vsc9959.c
78
REG(ANA_TABLES_VLANTIDX, 0x007f38),
drivers/net/dsa/ocelot/felix_vsc9959.c
79
REG(ANA_TABLES_ISDXACCESS, 0x007f3c),
drivers/net/dsa/ocelot/felix_vsc9959.c
80
REG(ANA_TABLES_ISDXTIDX, 0x007f40),
drivers/net/dsa/ocelot/felix_vsc9959.c
81
REG(ANA_TABLES_ENTRYLIM, 0x007f00),
drivers/net/dsa/ocelot/felix_vsc9959.c
82
REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44),
drivers/net/dsa/ocelot/felix_vsc9959.c
83
REG(ANA_TABLES_PTP_ID_LOW, 0x007f48),
drivers/net/dsa/ocelot/felix_vsc9959.c
84
REG(ANA_TABLES_STREAMACCESS, 0x007f4c),
drivers/net/dsa/ocelot/felix_vsc9959.c
85
REG(ANA_TABLES_STREAMTIDX, 0x007f50),
drivers/net/dsa/ocelot/felix_vsc9959.c
86
REG(ANA_TABLES_SEQ_HISTORY, 0x007f54),
drivers/net/dsa/ocelot/felix_vsc9959.c
87
REG(ANA_TABLES_SEQ_MASK, 0x007f58),
drivers/net/dsa/ocelot/felix_vsc9959.c
88
REG(ANA_TABLES_SFID_MASK, 0x007f5c),
drivers/net/dsa/ocelot/felix_vsc9959.c
89
REG(ANA_TABLES_SFIDACCESS, 0x007f60),
drivers/net/dsa/ocelot/felix_vsc9959.c
90
REG(ANA_TABLES_SFIDTIDX, 0x007f64),
drivers/net/dsa/ocelot/felix_vsc9959.c
91
REG(ANA_MSTI_STATE, 0x008600),
drivers/net/dsa/ocelot/felix_vsc9959.c
92
REG(ANA_OAM_UPM_LM_CNT, 0x008000),
drivers/net/dsa/ocelot/felix_vsc9959.c
93
REG(ANA_SG_ACCESS_CTRL, 0x008a64),
drivers/net/dsa/ocelot/felix_vsc9959.c
94
REG(ANA_SG_CONFIG_REG_1, 0x007fb0),
drivers/net/dsa/ocelot/felix_vsc9959.c
95
REG(ANA_SG_CONFIG_REG_2, 0x007fb4),
drivers/net/dsa/ocelot/felix_vsc9959.c
96
REG(ANA_SG_CONFIG_REG_3, 0x007fb8),
drivers/net/dsa/ocelot/felix_vsc9959.c
97
REG(ANA_SG_CONFIG_REG_4, 0x007fbc),
drivers/net/dsa/ocelot/felix_vsc9959.c
98
REG(ANA_SG_CONFIG_REG_5, 0x007fc0),
drivers/net/dsa/ocelot/felix_vsc9959.c
99
REG(ANA_SG_GCL_GS_CONFIG, 0x007f80),
drivers/net/dsa/ocelot/seville_vsc9953.c
100
REG(ANA_PORT_VCAP_CFG, 0x00000c),
drivers/net/dsa/ocelot/seville_vsc9953.c
101
REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x000010),
drivers/net/dsa/ocelot/seville_vsc9953.c
102
REG(ANA_PORT_VCAP_S2_CFG, 0x00001c),
drivers/net/dsa/ocelot/seville_vsc9953.c
103
REG(ANA_PORT_PCP_DEI_MAP, 0x000020),
drivers/net/dsa/ocelot/seville_vsc9953.c
104
REG(ANA_PORT_CPU_FWD_CFG, 0x000060),
drivers/net/dsa/ocelot/seville_vsc9953.c
105
REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x000064),
drivers/net/dsa/ocelot/seville_vsc9953.c
106
REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x000068),
drivers/net/dsa/ocelot/seville_vsc9953.c
107
REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00006c),
drivers/net/dsa/ocelot/seville_vsc9953.c
108
REG(ANA_PORT_PORT_CFG, 0x000070),
drivers/net/dsa/ocelot/seville_vsc9953.c
109
REG(ANA_PORT_POL_CFG, 0x000074),
drivers/net/dsa/ocelot/seville_vsc9953.c
114
REG(ANA_PFC_PFC_CFG, 0x00c000),
drivers/net/dsa/ocelot/seville_vsc9953.c
120
REG(ANA_AGGR_CFG, 0x00c600),
drivers/net/dsa/ocelot/seville_vsc9953.c
121
REG(ANA_CPUQ_CFG, 0x00c604),
drivers/net/dsa/ocelot/seville_vsc9953.c
123
REG(ANA_CPUQ_8021_CFG, 0x00c60c),
drivers/net/dsa/ocelot/seville_vsc9953.c
124
REG(ANA_DSCP_CFG, 0x00c64c),
drivers/net/dsa/ocelot/seville_vsc9953.c
125
REG(ANA_DSCP_REWR_CFG, 0x00c74c),
drivers/net/dsa/ocelot/seville_vsc9953.c
126
REG(ANA_VCAP_RNG_TYPE_CFG, 0x00c78c),
drivers/net/dsa/ocelot/seville_vsc9953.c
127
REG(ANA_VCAP_RNG_VAL_CFG, 0x00c7ac),
drivers/net/dsa/ocelot/seville_vsc9953.c
131
REG(ANA_DISCARD_CFG, 0x00c7d8),
drivers/net/dsa/ocelot/seville_vsc9953.c
132
REG(ANA_FID_CFG, 0x00c7dc),
drivers/net/dsa/ocelot/seville_vsc9953.c
133
REG(ANA_POL_PIR_CFG, 0x00a000),
drivers/net/dsa/ocelot/seville_vsc9953.c
134
REG(ANA_POL_CIR_CFG, 0x00a004),
drivers/net/dsa/ocelot/seville_vsc9953.c
135
REG(ANA_POL_MODE_CFG, 0x00a008),
drivers/net/dsa/ocelot/seville_vsc9953.c
136
REG(ANA_POL_PIR_STATE, 0x00a00c),
drivers/net/dsa/ocelot/seville_vsc9953.c
137
REG(ANA_POL_CIR_STATE, 0x00a010),
drivers/net/dsa/ocelot/seville_vsc9953.c
139
REG(ANA_POL_FLOWC, 0x00c280),
drivers/net/dsa/ocelot/seville_vsc9953.c
140
REG(ANA_POL_HYST, 0x00c2ec),
drivers/net/dsa/ocelot/seville_vsc9953.c
145
REG(QS_XTR_GRP_CFG, 0x000000),
drivers/net/dsa/ocelot/seville_vsc9953.c
146
REG(QS_XTR_RD, 0x000008),
drivers/net/dsa/ocelot/seville_vsc9953.c
147
REG(QS_XTR_FRM_PRUNING, 0x000010),
drivers/net/dsa/ocelot/seville_vsc9953.c
148
REG(QS_XTR_FLUSH, 0x000018),
drivers/net/dsa/ocelot/seville_vsc9953.c
149
REG(QS_XTR_DATA_PRESENT, 0x00001c),
drivers/net/dsa/ocelot/seville_vsc9953.c
150
REG(QS_XTR_CFG, 0x000020),
drivers/net/dsa/ocelot/seville_vsc9953.c
151
REG(QS_INJ_GRP_CFG, 0x000024),
drivers/net/dsa/ocelot/seville_vsc9953.c
152
REG(QS_INJ_WR, 0x00002c),
drivers/net/dsa/ocelot/seville_vsc9953.c
153
REG(QS_INJ_CTRL, 0x000034),
drivers/net/dsa/ocelot/seville_vsc9953.c
154
REG(QS_INJ_STATUS, 0x00003c),
drivers/net/dsa/ocelot/seville_vsc9953.c
155
REG(QS_INJ_ERR, 0x000040),
drivers/net/dsa/ocelot/seville_vsc9953.c
161
REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
drivers/net/dsa/ocelot/seville_vsc9953.c
162
REG(VCAP_CORE_MV_CFG, 0x000004),
drivers/net/dsa/ocelot/seville_vsc9953.c
164
REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
drivers/net/dsa/ocelot/seville_vsc9953.c
165
REG(VCAP_CACHE_MASK_DAT, 0x000108),
drivers/net/dsa/ocelot/seville_vsc9953.c
166
REG(VCAP_CACHE_ACTION_DAT, 0x000208),
drivers/net/dsa/ocelot/seville_vsc9953.c
167
REG(VCAP_CACHE_CNT_DAT, 0x000308),
drivers/net/dsa/ocelot/seville_vsc9953.c
168
REG(VCAP_CACHE_TG_DAT, 0x000388),
drivers/net/dsa/ocelot/seville_vsc9953.c
170
REG(VCAP_CONST_VCAP_VER, 0x000398),
drivers/net/dsa/ocelot/seville_vsc9953.c
171
REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
drivers/net/dsa/ocelot/seville_vsc9953.c
172
REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
drivers/net/dsa/ocelot/seville_vsc9953.c
173
REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
drivers/net/dsa/ocelot/seville_vsc9953.c
174
REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
drivers/net/dsa/ocelot/seville_vsc9953.c
175
REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
drivers/net/dsa/ocelot/seville_vsc9953.c
183
REG(QSYS_PORT_MODE, 0x003600),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_SWITCH_PORT_MODE, 0x003630),
drivers/net/dsa/ocelot/seville_vsc9953.c
185
REG(QSYS_STAT_CNT_CFG, 0x00365c),
drivers/net/dsa/ocelot/seville_vsc9953.c
186
REG(QSYS_EEE_CFG, 0x003660),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_EEE_THRES, 0x003688),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_IGR_NO_SHARING, 0x00368c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_EGR_NO_SHARING, 0x003690),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_SW_STATUS, 0x003694),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_EXT_CPU_CFG, 0x0036c0),
drivers/net/dsa/ocelot/seville_vsc9953.c
193
REG(QSYS_CPU_GROUP_MAP, 0x0036c8),
drivers/net/dsa/ocelot/seville_vsc9953.c
207
REG(QSYS_RED_PROFILE, 0x003724),
drivers/net/dsa/ocelot/seville_vsc9953.c
208
REG(QSYS_RES_QOS_MODE, 0x003764),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_RES_CFG, 0x004000),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_RES_STAT, 0x004004),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_EGR_DROP_MODE, 0x003768),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_EQ_CTRL, 0x00376c),
drivers/net/dsa/ocelot/seville_vsc9953.c
223
REG(QSYS_CIR_CFG, 0x000000),
drivers/net/dsa/ocelot/seville_vsc9953.c
225
REG(QSYS_SE_CFG, 0x000008),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(QSYS_SE_DWRR_CFG, 0x00000c),
drivers/net/dsa/ocelot/seville_vsc9953.c
229
REG(QSYS_CIR_STATE, 0x000044),
drivers/net/dsa/ocelot/seville_vsc9953.c
232
REG(QSYS_HSCH_MISC_CFG, 0x003774),
drivers/net/dsa/ocelot/seville_vsc9953.c
257
REG(REW_PORT_VLAN_CFG, 0x000000),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(REW_TAG_CFG, 0x000004),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(REW_PORT_CFG, 0x000008),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(REW_DSCP_CFG, 0x00000c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
drivers/net/dsa/ocelot/seville_vsc9953.c
265
REG(REW_DSCP_REMAP_DP1_CFG, 0x000610),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(REW_DSCP_REMAP_CFG, 0x000710),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_OCTETS, 0x000000),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_UNICAST, 0x000004),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_MULTICAST, 0x000008),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_SHORTS, 0x000010),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_JABBERS, 0x000018),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_64, 0x000024),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_65_127, 0x000028),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_128_255, 0x00002c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_256_511, 0x000030),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_512_1023, 0x000034),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_1024_1526, 0x000038),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_1527_MAX, 0x00003c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_PAUSE, 0x000040),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_CONTROL, 0x000044),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_LONGS, 0x000048),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_OCTETS, 0x000100),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_UNICAST, 0x000104),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_MULTICAST, 0x000108),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_BROADCAST, 0x00010c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_COLLISION, 0x000110),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_DROPS, 0x000114),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_PAUSE, 0x000118),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_64, 0x00011c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_65_127, 0x000120),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_128_255, 0x000124),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_256_511, 0x000128),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_512_1023, 0x00012c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_1024_1526, 0x000130),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_1527_MAX, 0x000134),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000138),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00013c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000140),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000144),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000148),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00014c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000150),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000154),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000158),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00015c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000160),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000164),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000168),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00016c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000170),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000174),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_TX_AGED, 0x000178),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_LOCAL, 0x000200),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_TAIL, 0x000204),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000208),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00020c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000210),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000214),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000218),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00021c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000220),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000224),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000228),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00022c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000230),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000234),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000238),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00023c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000240),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000244),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_RESET_CFG, 0x000318),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_VLAN_ETYPE_CFG, 0x000320),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_PORT_MODE, 0x000324),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_FRONT_PORT_MODE, 0x000354),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_FRM_AGING, 0x00037c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_STAT_CFG, 0x000380),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_PAUSE_CFG, 0x00044c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_PAUSE_TOT_CFG, 0x000478),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_ATOP, 0x00047c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_ATOP_TOT_CFG, 0x0004a8),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_MAC_FC_CFG, 0x0004ac),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(SYS_MMGT, 0x0004d4),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(GCB_SOFT_RST, 0x000008),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(GCB_MIIM_MII_STATUS, 0x0000ac),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(GCB_MIIM_MII_CMD, 0x0000b4),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(GCB_MIIM_MII_DATA, 0x0000b8),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_CLOCK_CFG, 0x0),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_PORT_MISC, 0x4),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_EEE_CFG, 0xc),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_ENA_CFG, 0x10),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_MODE_CFG, 0x14),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_MAXLEN_CFG, 0x18),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_TAGS_CFG, 0x1c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_ADV_CHK_CFG, 0x20),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_IFG_CFG, 0x24),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_HDX_CFG, 0x28),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_FC_MAC_LOW_CFG, 0x30),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x34),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(DEV_MAC_STICKY, 0x38),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_ADVLEARN, 0x00b500),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_VLANMASK, 0x00b504),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_ANAGEFIL, 0x00b50c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_ANEVENTS, 0x00b510),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_STORMLIMIT_BURST, 0x00b514),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_STORMLIMIT_CFG, 0x00b518),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_ISOLATED_PORTS, 0x00b528),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_COMMUNITY_PORTS, 0x00b52c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_AUTOAGE, 0x00b530),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_MACTOPTIONS, 0x00b534),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_LEARNDISC, 0x00b538),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_AGENCTRL, 0x00b53c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_MIRRORPORTS, 0x00b540),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_EMIRRORPORTS, 0x00b544),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_FLOODING, 0x00b548),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_FLOODING_IPMC, 0x00b54c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_SFLOW_CFG, 0x00b550),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_PORT_MODE, 0x00b57c),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_PGID_PGID, 0x00b600),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_TABLES_ANMOVED, 0x00b4ac),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_TABLES_MACHDATA, 0x00b4b0),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_TABLES_MACLDATA, 0x00b4b4),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_TABLES_MACACCESS, 0x00b4b8),
drivers/net/dsa/ocelot/seville_vsc9953.c
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REG(ANA_TABLES_MACTINDX, 0x00b4bc),
drivers/net/dsa/ocelot/seville_vsc9953.c
70
REG(ANA_TABLES_VLANACCESS, 0x00b4c0),
drivers/net/dsa/ocelot/seville_vsc9953.c
71
REG(ANA_TABLES_VLANTIDX, 0x00b4c4),
drivers/net/dsa/ocelot/seville_vsc9953.c
74
REG(ANA_TABLES_ENTRYLIM, 0x00b480),
drivers/net/dsa/ocelot/seville_vsc9953.c
97
REG(ANA_PORT_VLAN_CFG, 0x000000),
drivers/net/dsa/ocelot/seville_vsc9953.c
98
REG(ANA_PORT_DROP_CFG, 0x000004),
drivers/net/dsa/ocelot/seville_vsc9953.c
99
REG(ANA_PORT_QOS_CFG, 0x000008),
drivers/net/ethernet/apple/mace.h
12
REG(rcvfifo); /* receive FIFO */
drivers/net/ethernet/apple/mace.h
13
REG(xmtfifo); /* transmit FIFO */
drivers/net/ethernet/apple/mace.h
14
REG(xmtfc); /* transmit frame control */
drivers/net/ethernet/apple/mace.h
15
REG(xmtfs); /* transmit frame status */
drivers/net/ethernet/apple/mace.h
16
REG(xmtrc); /* transmit retry count */
drivers/net/ethernet/apple/mace.h
17
REG(rcvfc); /* receive frame control */
drivers/net/ethernet/apple/mace.h
18
REG(rcvfs); /* receive frame status (4 bytes) */
drivers/net/ethernet/apple/mace.h
19
REG(fifofc); /* FIFO frame count */
drivers/net/ethernet/apple/mace.h
20
REG(ir); /* interrupt register */
drivers/net/ethernet/apple/mace.h
21
REG(imr); /* interrupt mask register */
drivers/net/ethernet/apple/mace.h
22
REG(pr); /* poll register */
drivers/net/ethernet/apple/mace.h
23
REG(biucc); /* bus interface unit config control */
drivers/net/ethernet/apple/mace.h
24
REG(fifocc); /* FIFO configuration control */
drivers/net/ethernet/apple/mace.h
25
REG(maccc); /* medium access control config control */
drivers/net/ethernet/apple/mace.h
26
REG(plscc); /* phys layer signalling config control */
drivers/net/ethernet/apple/mace.h
27
REG(phycc); /* physical configuration control */
drivers/net/ethernet/apple/mace.h
28
REG(chipid_lo); /* chip ID, lsb */
drivers/net/ethernet/apple/mace.h
29
REG(chipid_hi); /* chip ID, msb */
drivers/net/ethernet/apple/mace.h
30
REG(iac); /* internal address config */
drivers/net/ethernet/apple/mace.h
31
REG(reg19);
drivers/net/ethernet/apple/mace.h
32
REG(ladrf); /* logical address filter (8 bytes) */
drivers/net/ethernet/apple/mace.h
33
REG(padr); /* physical address (6 bytes) */
drivers/net/ethernet/apple/mace.h
34
REG(reg22);
drivers/net/ethernet/apple/mace.h
35
REG(reg23);
drivers/net/ethernet/apple/mace.h
36
REG(mpc); /* missed packet count (clears when read) */
drivers/net/ethernet/apple/mace.h
37
REG(reg25);
drivers/net/ethernet/apple/mace.h
38
REG(rntpc); /* runt packet count (clears when read) */
drivers/net/ethernet/apple/mace.h
39
REG(rcvcc); /* recv collision count (clears when read) */
drivers/net/ethernet/apple/mace.h
40
REG(reg28);
drivers/net/ethernet/apple/mace.h
41
REG(utr); /* user test reg */
drivers/net/ethernet/apple/mace.h
42
REG(reg30);
drivers/net/ethernet/apple/mace.h
43
REG(reg31);
drivers/net/ethernet/broadcom/tg3.c
10963
#define TG3_STAT_ADD32(PSTAT, REG) \
drivers/net/ethernet/broadcom/tg3.c
10964
do { u32 __val = tr32(REG); \
drivers/net/ethernet/freescale/fs_enet/mac-fcc.c
67
#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
drivers/net/ethernet/freescale/fs_enet/mac-fcc.c
68
#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
drivers/net/ethernet/freescale/fs_enet/mii-fec.c
45
#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
drivers/net/ethernet/freescale/fs_enet/mii-fec.c
46
#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
drivers/net/ethernet/mscc/vsc7514_regs.c
100
REG(ANA_TABLES_ISDXTIDX, 0x008b50),
drivers/net/ethernet/mscc/vsc7514_regs.c
101
REG(ANA_TABLES_ENTRYLIM, 0x008b00),
drivers/net/ethernet/mscc/vsc7514_regs.c
102
REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54),
drivers/net/ethernet/mscc/vsc7514_regs.c
103
REG(ANA_TABLES_PTP_ID_LOW, 0x008b58),
drivers/net/ethernet/mscc/vsc7514_regs.c
104
REG(ANA_MSTI_STATE, 0x008e00),
drivers/net/ethernet/mscc/vsc7514_regs.c
105
REG(ANA_PORT_VLAN_CFG, 0x007000),
drivers/net/ethernet/mscc/vsc7514_regs.c
106
REG(ANA_PORT_DROP_CFG, 0x007004),
drivers/net/ethernet/mscc/vsc7514_regs.c
107
REG(ANA_PORT_QOS_CFG, 0x007008),
drivers/net/ethernet/mscc/vsc7514_regs.c
108
REG(ANA_PORT_VCAP_CFG, 0x00700c),
drivers/net/ethernet/mscc/vsc7514_regs.c
109
REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010),
drivers/net/ethernet/mscc/vsc7514_regs.c
110
REG(ANA_PORT_VCAP_S2_CFG, 0x00701c),
drivers/net/ethernet/mscc/vsc7514_regs.c
111
REG(ANA_PORT_PCP_DEI_MAP, 0x007020),
drivers/net/ethernet/mscc/vsc7514_regs.c
112
REG(ANA_PORT_CPU_FWD_CFG, 0x007060),
drivers/net/ethernet/mscc/vsc7514_regs.c
113
REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064),
drivers/net/ethernet/mscc/vsc7514_regs.c
114
REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068),
drivers/net/ethernet/mscc/vsc7514_regs.c
115
REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c),
drivers/net/ethernet/mscc/vsc7514_regs.c
116
REG(ANA_PORT_PORT_CFG, 0x007070),
drivers/net/ethernet/mscc/vsc7514_regs.c
117
REG(ANA_PORT_POL_CFG, 0x007074),
drivers/net/ethernet/mscc/vsc7514_regs.c
118
REG(ANA_PORT_PTP_CFG, 0x007078),
drivers/net/ethernet/mscc/vsc7514_regs.c
119
REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c),
drivers/net/ethernet/mscc/vsc7514_regs.c
120
REG(ANA_OAM_UPM_LM_CNT, 0x007c00),
drivers/net/ethernet/mscc/vsc7514_regs.c
121
REG(ANA_PORT_PTP_DLY2_CFG, 0x007080),
drivers/net/ethernet/mscc/vsc7514_regs.c
122
REG(ANA_PFC_PFC_CFG, 0x008800),
drivers/net/ethernet/mscc/vsc7514_regs.c
123
REG(ANA_PFC_PFC_TIMER, 0x008804),
drivers/net/ethernet/mscc/vsc7514_regs.c
124
REG(ANA_IPT_OAM_MEP_CFG, 0x008000),
drivers/net/ethernet/mscc/vsc7514_regs.c
125
REG(ANA_IPT_IPT, 0x008004),
drivers/net/ethernet/mscc/vsc7514_regs.c
126
REG(ANA_PPT_PPT, 0x008ac0),
drivers/net/ethernet/mscc/vsc7514_regs.c
127
REG(ANA_FID_MAP_FID_MAP, 0x000000),
drivers/net/ethernet/mscc/vsc7514_regs.c
128
REG(ANA_AGGR_CFG, 0x0090b4),
drivers/net/ethernet/mscc/vsc7514_regs.c
129
REG(ANA_CPUQ_CFG, 0x0090b8),
drivers/net/ethernet/mscc/vsc7514_regs.c
130
REG(ANA_CPUQ_CFG2, 0x0090bc),
drivers/net/ethernet/mscc/vsc7514_regs.c
131
REG(ANA_CPUQ_8021_CFG, 0x0090c0),
drivers/net/ethernet/mscc/vsc7514_regs.c
132
REG(ANA_DSCP_CFG, 0x009100),
drivers/net/ethernet/mscc/vsc7514_regs.c
133
REG(ANA_DSCP_REWR_CFG, 0x009200),
drivers/net/ethernet/mscc/vsc7514_regs.c
134
REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240),
drivers/net/ethernet/mscc/vsc7514_regs.c
135
REG(ANA_VCAP_RNG_VAL_CFG, 0x009260),
drivers/net/ethernet/mscc/vsc7514_regs.c
136
REG(ANA_VRAP_CFG, 0x009280),
drivers/net/ethernet/mscc/vsc7514_regs.c
137
REG(ANA_VRAP_HDR_DATA, 0x009284),
drivers/net/ethernet/mscc/vsc7514_regs.c
138
REG(ANA_VRAP_HDR_MASK, 0x009288),
drivers/net/ethernet/mscc/vsc7514_regs.c
139
REG(ANA_DISCARD_CFG, 0x00928c),
drivers/net/ethernet/mscc/vsc7514_regs.c
140
REG(ANA_FID_CFG, 0x009290),
drivers/net/ethernet/mscc/vsc7514_regs.c
141
REG(ANA_POL_PIR_CFG, 0x004000),
drivers/net/ethernet/mscc/vsc7514_regs.c
142
REG(ANA_POL_CIR_CFG, 0x004004),
drivers/net/ethernet/mscc/vsc7514_regs.c
143
REG(ANA_POL_MODE_CFG, 0x004008),
drivers/net/ethernet/mscc/vsc7514_regs.c
144
REG(ANA_POL_PIR_STATE, 0x00400c),
drivers/net/ethernet/mscc/vsc7514_regs.c
145
REG(ANA_POL_CIR_STATE, 0x004010),
drivers/net/ethernet/mscc/vsc7514_regs.c
146
REG(ANA_POL_STATE, 0x004014),
drivers/net/ethernet/mscc/vsc7514_regs.c
147
REG(ANA_POL_FLOWC, 0x008b80),
drivers/net/ethernet/mscc/vsc7514_regs.c
148
REG(ANA_POL_HYST, 0x008bec),
drivers/net/ethernet/mscc/vsc7514_regs.c
149
REG(ANA_POL_MISC_CFG, 0x008bf0),
drivers/net/ethernet/mscc/vsc7514_regs.c
153
REG(QS_XTR_GRP_CFG, 0x000000),
drivers/net/ethernet/mscc/vsc7514_regs.c
154
REG(QS_XTR_RD, 0x000008),
drivers/net/ethernet/mscc/vsc7514_regs.c
155
REG(QS_XTR_FRM_PRUNING, 0x000010),
drivers/net/ethernet/mscc/vsc7514_regs.c
156
REG(QS_XTR_FLUSH, 0x000018),
drivers/net/ethernet/mscc/vsc7514_regs.c
157
REG(QS_XTR_DATA_PRESENT, 0x00001c),
drivers/net/ethernet/mscc/vsc7514_regs.c
158
REG(QS_XTR_CFG, 0x000020),
drivers/net/ethernet/mscc/vsc7514_regs.c
159
REG(QS_INJ_GRP_CFG, 0x000024),
drivers/net/ethernet/mscc/vsc7514_regs.c
160
REG(QS_INJ_WR, 0x00002c),
drivers/net/ethernet/mscc/vsc7514_regs.c
161
REG(QS_INJ_CTRL, 0x000034),
drivers/net/ethernet/mscc/vsc7514_regs.c
162
REG(QS_INJ_STATUS, 0x00003c),
drivers/net/ethernet/mscc/vsc7514_regs.c
163
REG(QS_INJ_ERR, 0x000040),
drivers/net/ethernet/mscc/vsc7514_regs.c
164
REG(QS_INH_DBG, 0x000048),
drivers/net/ethernet/mscc/vsc7514_regs.c
168
REG(QSYS_PORT_MODE, 0x011200),
drivers/net/ethernet/mscc/vsc7514_regs.c
169
REG(QSYS_SWITCH_PORT_MODE, 0x011234),
drivers/net/ethernet/mscc/vsc7514_regs.c
170
REG(QSYS_STAT_CNT_CFG, 0x011264),
drivers/net/ethernet/mscc/vsc7514_regs.c
171
REG(QSYS_EEE_CFG, 0x011268),
drivers/net/ethernet/mscc/vsc7514_regs.c
172
REG(QSYS_EEE_THRES, 0x011294),
drivers/net/ethernet/mscc/vsc7514_regs.c
173
REG(QSYS_IGR_NO_SHARING, 0x011298),
drivers/net/ethernet/mscc/vsc7514_regs.c
174
REG(QSYS_EGR_NO_SHARING, 0x01129c),
drivers/net/ethernet/mscc/vsc7514_regs.c
175
REG(QSYS_SW_STATUS, 0x0112a0),
drivers/net/ethernet/mscc/vsc7514_regs.c
176
REG(QSYS_EXT_CPU_CFG, 0x0112d0),
drivers/net/ethernet/mscc/vsc7514_regs.c
177
REG(QSYS_PAD_CFG, 0x0112d4),
drivers/net/ethernet/mscc/vsc7514_regs.c
178
REG(QSYS_CPU_GROUP_MAP, 0x0112d8),
drivers/net/ethernet/mscc/vsc7514_regs.c
179
REG(QSYS_QMAP, 0x0112dc),
drivers/net/ethernet/mscc/vsc7514_regs.c
180
REG(QSYS_ISDX_SGRP, 0x011400),
drivers/net/ethernet/mscc/vsc7514_regs.c
181
REG(QSYS_TIMED_FRAME_ENTRY, 0x014000),
drivers/net/ethernet/mscc/vsc7514_regs.c
182
REG(QSYS_TFRM_MISC, 0x011310),
drivers/net/ethernet/mscc/vsc7514_regs.c
183
REG(QSYS_TFRM_PORT_DLY, 0x011314),
drivers/net/ethernet/mscc/vsc7514_regs.c
184
REG(QSYS_TFRM_TIMER_CFG_1, 0x011318),
drivers/net/ethernet/mscc/vsc7514_regs.c
185
REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c),
drivers/net/ethernet/mscc/vsc7514_regs.c
186
REG(QSYS_TFRM_TIMER_CFG_3, 0x011320),
drivers/net/ethernet/mscc/vsc7514_regs.c
187
REG(QSYS_TFRM_TIMER_CFG_4, 0x011324),
drivers/net/ethernet/mscc/vsc7514_regs.c
188
REG(QSYS_TFRM_TIMER_CFG_5, 0x011328),
drivers/net/ethernet/mscc/vsc7514_regs.c
189
REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c),
drivers/net/ethernet/mscc/vsc7514_regs.c
190
REG(QSYS_TFRM_TIMER_CFG_7, 0x011330),
drivers/net/ethernet/mscc/vsc7514_regs.c
191
REG(QSYS_TFRM_TIMER_CFG_8, 0x011334),
drivers/net/ethernet/mscc/vsc7514_regs.c
192
REG(QSYS_RED_PROFILE, 0x011338),
drivers/net/ethernet/mscc/vsc7514_regs.c
193
REG(QSYS_RES_QOS_MODE, 0x011378),
drivers/net/ethernet/mscc/vsc7514_regs.c
194
REG(QSYS_RES_CFG, 0x012000),
drivers/net/ethernet/mscc/vsc7514_regs.c
195
REG(QSYS_RES_STAT, 0x012004),
drivers/net/ethernet/mscc/vsc7514_regs.c
196
REG(QSYS_EGR_DROP_MODE, 0x01137c),
drivers/net/ethernet/mscc/vsc7514_regs.c
197
REG(QSYS_EQ_CTRL, 0x011380),
drivers/net/ethernet/mscc/vsc7514_regs.c
198
REG(QSYS_EVENTS_CORE, 0x011384),
drivers/net/ethernet/mscc/vsc7514_regs.c
199
REG(QSYS_CIR_CFG, 0x000000),
drivers/net/ethernet/mscc/vsc7514_regs.c
200
REG(QSYS_EIR_CFG, 0x000004),
drivers/net/ethernet/mscc/vsc7514_regs.c
201
REG(QSYS_SE_CFG, 0x000008),
drivers/net/ethernet/mscc/vsc7514_regs.c
202
REG(QSYS_SE_DWRR_CFG, 0x00000c),
drivers/net/ethernet/mscc/vsc7514_regs.c
203
REG(QSYS_SE_CONNECT, 0x00003c),
drivers/net/ethernet/mscc/vsc7514_regs.c
204
REG(QSYS_SE_DLB_SENSE, 0x000040),
drivers/net/ethernet/mscc/vsc7514_regs.c
205
REG(QSYS_CIR_STATE, 0x000044),
drivers/net/ethernet/mscc/vsc7514_regs.c
206
REG(QSYS_EIR_STATE, 0x000048),
drivers/net/ethernet/mscc/vsc7514_regs.c
207
REG(QSYS_SE_STATE, 0x00004c),
drivers/net/ethernet/mscc/vsc7514_regs.c
208
REG(QSYS_HSCH_MISC_CFG, 0x011388),
drivers/net/ethernet/mscc/vsc7514_regs.c
212
REG(REW_PORT_VLAN_CFG, 0x000000),
drivers/net/ethernet/mscc/vsc7514_regs.c
213
REG(REW_TAG_CFG, 0x000004),
drivers/net/ethernet/mscc/vsc7514_regs.c
214
REG(REW_PORT_CFG, 0x000008),
drivers/net/ethernet/mscc/vsc7514_regs.c
215
REG(REW_DSCP_CFG, 0x00000c),
drivers/net/ethernet/mscc/vsc7514_regs.c
216
REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
drivers/net/ethernet/mscc/vsc7514_regs.c
217
REG(REW_PTP_CFG, 0x000050),
drivers/net/ethernet/mscc/vsc7514_regs.c
218
REG(REW_PTP_DLY1_CFG, 0x000054),
drivers/net/ethernet/mscc/vsc7514_regs.c
219
REG(REW_DSCP_REMAP_DP1_CFG, 0x000690),
drivers/net/ethernet/mscc/vsc7514_regs.c
220
REG(REW_DSCP_REMAP_CFG, 0x000790),
drivers/net/ethernet/mscc/vsc7514_regs.c
221
REG(REW_STAT_CFG, 0x000890),
drivers/net/ethernet/mscc/vsc7514_regs.c
222
REG(REW_PPT, 0x000680),
drivers/net/ethernet/mscc/vsc7514_regs.c
226
REG(SYS_COUNT_RX_OCTETS, 0x000000),
drivers/net/ethernet/mscc/vsc7514_regs.c
227
REG(SYS_COUNT_RX_UNICAST, 0x000004),
drivers/net/ethernet/mscc/vsc7514_regs.c
228
REG(SYS_COUNT_RX_MULTICAST, 0x000008),
drivers/net/ethernet/mscc/vsc7514_regs.c
229
REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
drivers/net/ethernet/mscc/vsc7514_regs.c
230
REG(SYS_COUNT_RX_SHORTS, 0x000010),
drivers/net/ethernet/mscc/vsc7514_regs.c
231
REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
drivers/net/ethernet/mscc/vsc7514_regs.c
232
REG(SYS_COUNT_RX_JABBERS, 0x000018),
drivers/net/ethernet/mscc/vsc7514_regs.c
233
REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
drivers/net/ethernet/mscc/vsc7514_regs.c
234
REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
drivers/net/ethernet/mscc/vsc7514_regs.c
235
REG(SYS_COUNT_RX_64, 0x000024),
drivers/net/ethernet/mscc/vsc7514_regs.c
236
REG(SYS_COUNT_RX_65_127, 0x000028),
drivers/net/ethernet/mscc/vsc7514_regs.c
237
REG(SYS_COUNT_RX_128_255, 0x00002c),
drivers/net/ethernet/mscc/vsc7514_regs.c
238
REG(SYS_COUNT_RX_256_511, 0x000030),
drivers/net/ethernet/mscc/vsc7514_regs.c
239
REG(SYS_COUNT_RX_512_1023, 0x000034),
drivers/net/ethernet/mscc/vsc7514_regs.c
240
REG(SYS_COUNT_RX_1024_1526, 0x000038),
drivers/net/ethernet/mscc/vsc7514_regs.c
241
REG(SYS_COUNT_RX_1527_MAX, 0x00003c),
drivers/net/ethernet/mscc/vsc7514_regs.c
242
REG(SYS_COUNT_RX_PAUSE, 0x000040),
drivers/net/ethernet/mscc/vsc7514_regs.c
243
REG(SYS_COUNT_RX_CONTROL, 0x000044),
drivers/net/ethernet/mscc/vsc7514_regs.c
244
REG(SYS_COUNT_RX_LONGS, 0x000048),
drivers/net/ethernet/mscc/vsc7514_regs.c
245
REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c),
drivers/net/ethernet/mscc/vsc7514_regs.c
246
REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050),
drivers/net/ethernet/mscc/vsc7514_regs.c
247
REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054),
drivers/net/ethernet/mscc/vsc7514_regs.c
248
REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058),
drivers/net/ethernet/mscc/vsc7514_regs.c
249
REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c),
drivers/net/ethernet/mscc/vsc7514_regs.c
250
REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060),
drivers/net/ethernet/mscc/vsc7514_regs.c
251
REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064),
drivers/net/ethernet/mscc/vsc7514_regs.c
252
REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068),
drivers/net/ethernet/mscc/vsc7514_regs.c
253
REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c),
drivers/net/ethernet/mscc/vsc7514_regs.c
254
REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070),
drivers/net/ethernet/mscc/vsc7514_regs.c
255
REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074),
drivers/net/ethernet/mscc/vsc7514_regs.c
256
REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078),
drivers/net/ethernet/mscc/vsc7514_regs.c
257
REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c),
drivers/net/ethernet/mscc/vsc7514_regs.c
258
REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080),
drivers/net/ethernet/mscc/vsc7514_regs.c
259
REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084),
drivers/net/ethernet/mscc/vsc7514_regs.c
260
REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088),
drivers/net/ethernet/mscc/vsc7514_regs.c
261
REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c),
drivers/net/ethernet/mscc/vsc7514_regs.c
262
REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090),
drivers/net/ethernet/mscc/vsc7514_regs.c
263
REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094),
drivers/net/ethernet/mscc/vsc7514_regs.c
264
REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098),
drivers/net/ethernet/mscc/vsc7514_regs.c
265
REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c),
drivers/net/ethernet/mscc/vsc7514_regs.c
266
REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0),
drivers/net/ethernet/mscc/vsc7514_regs.c
267
REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4),
drivers/net/ethernet/mscc/vsc7514_regs.c
268
REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8),
drivers/net/ethernet/mscc/vsc7514_regs.c
269
REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac),
drivers/net/ethernet/mscc/vsc7514_regs.c
270
REG(SYS_COUNT_TX_OCTETS, 0x000100),
drivers/net/ethernet/mscc/vsc7514_regs.c
271
REG(SYS_COUNT_TX_UNICAST, 0x000104),
drivers/net/ethernet/mscc/vsc7514_regs.c
272
REG(SYS_COUNT_TX_MULTICAST, 0x000108),
drivers/net/ethernet/mscc/vsc7514_regs.c
273
REG(SYS_COUNT_TX_BROADCAST, 0x00010c),
drivers/net/ethernet/mscc/vsc7514_regs.c
274
REG(SYS_COUNT_TX_COLLISION, 0x000110),
drivers/net/ethernet/mscc/vsc7514_regs.c
275
REG(SYS_COUNT_TX_DROPS, 0x000114),
drivers/net/ethernet/mscc/vsc7514_regs.c
276
REG(SYS_COUNT_TX_PAUSE, 0x000118),
drivers/net/ethernet/mscc/vsc7514_regs.c
277
REG(SYS_COUNT_TX_64, 0x00011c),
drivers/net/ethernet/mscc/vsc7514_regs.c
278
REG(SYS_COUNT_TX_65_127, 0x000120),
drivers/net/ethernet/mscc/vsc7514_regs.c
279
REG(SYS_COUNT_TX_128_255, 0x000124),
drivers/net/ethernet/mscc/vsc7514_regs.c
280
REG(SYS_COUNT_TX_256_511, 0x000128),
drivers/net/ethernet/mscc/vsc7514_regs.c
281
REG(SYS_COUNT_TX_512_1023, 0x00012c),
drivers/net/ethernet/mscc/vsc7514_regs.c
282
REG(SYS_COUNT_TX_1024_1526, 0x000130),
drivers/net/ethernet/mscc/vsc7514_regs.c
283
REG(SYS_COUNT_TX_1527_MAX, 0x000134),
drivers/net/ethernet/mscc/vsc7514_regs.c
284
REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000138),
drivers/net/ethernet/mscc/vsc7514_regs.c
285
REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00013c),
drivers/net/ethernet/mscc/vsc7514_regs.c
286
REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000140),
drivers/net/ethernet/mscc/vsc7514_regs.c
287
REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000144),
drivers/net/ethernet/mscc/vsc7514_regs.c
288
REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000148),
drivers/net/ethernet/mscc/vsc7514_regs.c
289
REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00014c),
drivers/net/ethernet/mscc/vsc7514_regs.c
290
REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000150),
drivers/net/ethernet/mscc/vsc7514_regs.c
291
REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000154),
drivers/net/ethernet/mscc/vsc7514_regs.c
292
REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000158),
drivers/net/ethernet/mscc/vsc7514_regs.c
293
REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00015c),
drivers/net/ethernet/mscc/vsc7514_regs.c
294
REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000160),
drivers/net/ethernet/mscc/vsc7514_regs.c
295
REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000164),
drivers/net/ethernet/mscc/vsc7514_regs.c
296
REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000168),
drivers/net/ethernet/mscc/vsc7514_regs.c
297
REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00016c),
drivers/net/ethernet/mscc/vsc7514_regs.c
298
REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000170),
drivers/net/ethernet/mscc/vsc7514_regs.c
299
REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000174),
drivers/net/ethernet/mscc/vsc7514_regs.c
300
REG(SYS_COUNT_TX_AGED, 0x000178),
drivers/net/ethernet/mscc/vsc7514_regs.c
301
REG(SYS_COUNT_DROP_LOCAL, 0x000200),
drivers/net/ethernet/mscc/vsc7514_regs.c
302
REG(SYS_COUNT_DROP_TAIL, 0x000204),
drivers/net/ethernet/mscc/vsc7514_regs.c
303
REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000208),
drivers/net/ethernet/mscc/vsc7514_regs.c
304
REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00020c),
drivers/net/ethernet/mscc/vsc7514_regs.c
305
REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000210),
drivers/net/ethernet/mscc/vsc7514_regs.c
306
REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000214),
drivers/net/ethernet/mscc/vsc7514_regs.c
307
REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000218),
drivers/net/ethernet/mscc/vsc7514_regs.c
308
REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00021c),
drivers/net/ethernet/mscc/vsc7514_regs.c
309
REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000220),
drivers/net/ethernet/mscc/vsc7514_regs.c
310
REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000224),
drivers/net/ethernet/mscc/vsc7514_regs.c
311
REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000228),
drivers/net/ethernet/mscc/vsc7514_regs.c
312
REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00022c),
drivers/net/ethernet/mscc/vsc7514_regs.c
313
REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000230),
drivers/net/ethernet/mscc/vsc7514_regs.c
314
REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000234),
drivers/net/ethernet/mscc/vsc7514_regs.c
315
REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000238),
drivers/net/ethernet/mscc/vsc7514_regs.c
316
REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00023c),
drivers/net/ethernet/mscc/vsc7514_regs.c
317
REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000240),
drivers/net/ethernet/mscc/vsc7514_regs.c
318
REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000244),
drivers/net/ethernet/mscc/vsc7514_regs.c
319
REG(SYS_RESET_CFG, 0x000508),
drivers/net/ethernet/mscc/vsc7514_regs.c
320
REG(SYS_CMID, 0x00050c),
drivers/net/ethernet/mscc/vsc7514_regs.c
321
REG(SYS_VLAN_ETYPE_CFG, 0x000510),
drivers/net/ethernet/mscc/vsc7514_regs.c
322
REG(SYS_PORT_MODE, 0x000514),
drivers/net/ethernet/mscc/vsc7514_regs.c
323
REG(SYS_FRONT_PORT_MODE, 0x000548),
drivers/net/ethernet/mscc/vsc7514_regs.c
324
REG(SYS_FRM_AGING, 0x000574),
drivers/net/ethernet/mscc/vsc7514_regs.c
325
REG(SYS_STAT_CFG, 0x000578),
drivers/net/ethernet/mscc/vsc7514_regs.c
326
REG(SYS_SW_STATUS, 0x00057c),
drivers/net/ethernet/mscc/vsc7514_regs.c
327
REG(SYS_MISC_CFG, 0x0005ac),
drivers/net/ethernet/mscc/vsc7514_regs.c
328
REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0),
drivers/net/ethernet/mscc/vsc7514_regs.c
329
REG(SYS_REW_MAC_LOW_CFG, 0x0005dc),
drivers/net/ethernet/mscc/vsc7514_regs.c
330
REG(SYS_CM_ADDR, 0x000500),
drivers/net/ethernet/mscc/vsc7514_regs.c
331
REG(SYS_CM_DATA, 0x000504),
drivers/net/ethernet/mscc/vsc7514_regs.c
332
REG(SYS_PAUSE_CFG, 0x000608),
drivers/net/ethernet/mscc/vsc7514_regs.c
333
REG(SYS_PAUSE_TOT_CFG, 0x000638),
drivers/net/ethernet/mscc/vsc7514_regs.c
334
REG(SYS_ATOP, 0x00063c),
drivers/net/ethernet/mscc/vsc7514_regs.c
335
REG(SYS_ATOP_TOT_CFG, 0x00066c),
drivers/net/ethernet/mscc/vsc7514_regs.c
336
REG(SYS_MAC_FC_CFG, 0x000670),
drivers/net/ethernet/mscc/vsc7514_regs.c
337
REG(SYS_MMGT, 0x00069c),
drivers/net/ethernet/mscc/vsc7514_regs.c
338
REG(SYS_MMGT_FAST, 0x0006a0),
drivers/net/ethernet/mscc/vsc7514_regs.c
339
REG(SYS_EVENTS_DIF, 0x0006a4),
drivers/net/ethernet/mscc/vsc7514_regs.c
340
REG(SYS_EVENTS_CORE, 0x0006b4),
drivers/net/ethernet/mscc/vsc7514_regs.c
341
REG(SYS_PTP_STATUS, 0x0006b8),
drivers/net/ethernet/mscc/vsc7514_regs.c
342
REG(SYS_PTP_TXSTAMP, 0x0006bc),
drivers/net/ethernet/mscc/vsc7514_regs.c
343
REG(SYS_PTP_NXT, 0x0006c0),
drivers/net/ethernet/mscc/vsc7514_regs.c
344
REG(SYS_PTP_CFG, 0x0006c4),
drivers/net/ethernet/mscc/vsc7514_regs.c
349
REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
drivers/net/ethernet/mscc/vsc7514_regs.c
350
REG(VCAP_CORE_MV_CFG, 0x000004),
drivers/net/ethernet/mscc/vsc7514_regs.c
352
REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
drivers/net/ethernet/mscc/vsc7514_regs.c
353
REG(VCAP_CACHE_MASK_DAT, 0x000108),
drivers/net/ethernet/mscc/vsc7514_regs.c
354
REG(VCAP_CACHE_ACTION_DAT, 0x000208),
drivers/net/ethernet/mscc/vsc7514_regs.c
355
REG(VCAP_CACHE_CNT_DAT, 0x000308),
drivers/net/ethernet/mscc/vsc7514_regs.c
356
REG(VCAP_CACHE_TG_DAT, 0x000388),
drivers/net/ethernet/mscc/vsc7514_regs.c
358
REG(VCAP_CONST_VCAP_VER, 0x000398),
drivers/net/ethernet/mscc/vsc7514_regs.c
359
REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
drivers/net/ethernet/mscc/vsc7514_regs.c
360
REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
drivers/net/ethernet/mscc/vsc7514_regs.c
361
REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
drivers/net/ethernet/mscc/vsc7514_regs.c
362
REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
drivers/net/ethernet/mscc/vsc7514_regs.c
363
REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
drivers/net/ethernet/mscc/vsc7514_regs.c
364
REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
drivers/net/ethernet/mscc/vsc7514_regs.c
365
REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
drivers/net/ethernet/mscc/vsc7514_regs.c
366
REG(VCAP_CONST_CORE_CNT, 0x0003b8),
drivers/net/ethernet/mscc/vsc7514_regs.c
367
REG(VCAP_CONST_IF_CNT, 0x0003bc),
drivers/net/ethernet/mscc/vsc7514_regs.c
371
REG(PTP_PIN_CFG, 0x000000),
drivers/net/ethernet/mscc/vsc7514_regs.c
372
REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
drivers/net/ethernet/mscc/vsc7514_regs.c
373
REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
drivers/net/ethernet/mscc/vsc7514_regs.c
374
REG(PTP_PIN_TOD_NSEC, 0x00000c),
drivers/net/ethernet/mscc/vsc7514_regs.c
375
REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
drivers/net/ethernet/mscc/vsc7514_regs.c
376
REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
drivers/net/ethernet/mscc/vsc7514_regs.c
377
REG(PTP_CFG_MISC, 0x0000a0),
drivers/net/ethernet/mscc/vsc7514_regs.c
378
REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
drivers/net/ethernet/mscc/vsc7514_regs.c
379
REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
drivers/net/ethernet/mscc/vsc7514_regs.c
383
REG(DEV_CLOCK_CFG, 0x0),
drivers/net/ethernet/mscc/vsc7514_regs.c
384
REG(DEV_PORT_MISC, 0x4),
drivers/net/ethernet/mscc/vsc7514_regs.c
385
REG(DEV_EVENTS, 0x8),
drivers/net/ethernet/mscc/vsc7514_regs.c
386
REG(DEV_EEE_CFG, 0xc),
drivers/net/ethernet/mscc/vsc7514_regs.c
387
REG(DEV_RX_PATH_DELAY, 0x10),
drivers/net/ethernet/mscc/vsc7514_regs.c
388
REG(DEV_TX_PATH_DELAY, 0x14),
drivers/net/ethernet/mscc/vsc7514_regs.c
389
REG(DEV_PTP_PREDICT_CFG, 0x18),
drivers/net/ethernet/mscc/vsc7514_regs.c
390
REG(DEV_MAC_ENA_CFG, 0x1c),
drivers/net/ethernet/mscc/vsc7514_regs.c
391
REG(DEV_MAC_MODE_CFG, 0x20),
drivers/net/ethernet/mscc/vsc7514_regs.c
392
REG(DEV_MAC_MAXLEN_CFG, 0x24),
drivers/net/ethernet/mscc/vsc7514_regs.c
393
REG(DEV_MAC_TAGS_CFG, 0x28),
drivers/net/ethernet/mscc/vsc7514_regs.c
394
REG(DEV_MAC_ADV_CHK_CFG, 0x2c),
drivers/net/ethernet/mscc/vsc7514_regs.c
395
REG(DEV_MAC_IFG_CFG, 0x30),
drivers/net/ethernet/mscc/vsc7514_regs.c
396
REG(DEV_MAC_HDX_CFG, 0x34),
drivers/net/ethernet/mscc/vsc7514_regs.c
397
REG(DEV_MAC_DBG_CFG, 0x38),
drivers/net/ethernet/mscc/vsc7514_regs.c
398
REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c),
drivers/net/ethernet/mscc/vsc7514_regs.c
399
REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40),
drivers/net/ethernet/mscc/vsc7514_regs.c
400
REG(DEV_MAC_STICKY, 0x44),
drivers/net/ethernet/mscc/vsc7514_regs.c
401
REG(PCS1G_CFG, 0x48),
drivers/net/ethernet/mscc/vsc7514_regs.c
402
REG(PCS1G_MODE_CFG, 0x4c),
drivers/net/ethernet/mscc/vsc7514_regs.c
403
REG(PCS1G_SD_CFG, 0x50),
drivers/net/ethernet/mscc/vsc7514_regs.c
404
REG(PCS1G_ANEG_CFG, 0x54),
drivers/net/ethernet/mscc/vsc7514_regs.c
405
REG(PCS1G_ANEG_NP_CFG, 0x58),
drivers/net/ethernet/mscc/vsc7514_regs.c
406
REG(PCS1G_LB_CFG, 0x5c),
drivers/net/ethernet/mscc/vsc7514_regs.c
407
REG(PCS1G_DBG_CFG, 0x60),
drivers/net/ethernet/mscc/vsc7514_regs.c
408
REG(PCS1G_CDET_CFG, 0x64),
drivers/net/ethernet/mscc/vsc7514_regs.c
409
REG(PCS1G_ANEG_STATUS, 0x68),
drivers/net/ethernet/mscc/vsc7514_regs.c
410
REG(PCS1G_ANEG_NP_STATUS, 0x6c),
drivers/net/ethernet/mscc/vsc7514_regs.c
411
REG(PCS1G_LINK_STATUS, 0x70),
drivers/net/ethernet/mscc/vsc7514_regs.c
412
REG(PCS1G_LINK_DOWN_CNT, 0x74),
drivers/net/ethernet/mscc/vsc7514_regs.c
413
REG(PCS1G_STICKY, 0x78),
drivers/net/ethernet/mscc/vsc7514_regs.c
414
REG(PCS1G_DEBUG_STATUS, 0x7c),
drivers/net/ethernet/mscc/vsc7514_regs.c
415
REG(PCS1G_LPI_CFG, 0x80),
drivers/net/ethernet/mscc/vsc7514_regs.c
416
REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84),
drivers/net/ethernet/mscc/vsc7514_regs.c
417
REG(PCS1G_LPI_STATUS, 0x88),
drivers/net/ethernet/mscc/vsc7514_regs.c
418
REG(PCS1G_TSTPAT_MODE_CFG, 0x8c),
drivers/net/ethernet/mscc/vsc7514_regs.c
419
REG(PCS1G_TSTPAT_STATUS, 0x90),
drivers/net/ethernet/mscc/vsc7514_regs.c
420
REG(DEV_PCS_FX100_CFG, 0x94),
drivers/net/ethernet/mscc/vsc7514_regs.c
421
REG(DEV_PCS_FX100_STATUS, 0x98),
drivers/net/ethernet/mscc/vsc7514_regs.c
72
REG(ANA_ADVLEARN, 0x009000),
drivers/net/ethernet/mscc/vsc7514_regs.c
73
REG(ANA_VLANMASK, 0x009004),
drivers/net/ethernet/mscc/vsc7514_regs.c
74
REG(ANA_PORT_B_DOMAIN, 0x009008),
drivers/net/ethernet/mscc/vsc7514_regs.c
75
REG(ANA_ANAGEFIL, 0x00900c),
drivers/net/ethernet/mscc/vsc7514_regs.c
76
REG(ANA_ANEVENTS, 0x009010),
drivers/net/ethernet/mscc/vsc7514_regs.c
77
REG(ANA_STORMLIMIT_BURST, 0x009014),
drivers/net/ethernet/mscc/vsc7514_regs.c
78
REG(ANA_STORMLIMIT_CFG, 0x009018),
drivers/net/ethernet/mscc/vsc7514_regs.c
79
REG(ANA_ISOLATED_PORTS, 0x009028),
drivers/net/ethernet/mscc/vsc7514_regs.c
80
REG(ANA_COMMUNITY_PORTS, 0x00902c),
drivers/net/ethernet/mscc/vsc7514_regs.c
81
REG(ANA_AUTOAGE, 0x009030),
drivers/net/ethernet/mscc/vsc7514_regs.c
82
REG(ANA_MACTOPTIONS, 0x009034),
drivers/net/ethernet/mscc/vsc7514_regs.c
83
REG(ANA_LEARNDISC, 0x009038),
drivers/net/ethernet/mscc/vsc7514_regs.c
84
REG(ANA_AGENCTRL, 0x00903c),
drivers/net/ethernet/mscc/vsc7514_regs.c
85
REG(ANA_MIRRORPORTS, 0x009040),
drivers/net/ethernet/mscc/vsc7514_regs.c
86
REG(ANA_EMIRRORPORTS, 0x009044),
drivers/net/ethernet/mscc/vsc7514_regs.c
87
REG(ANA_FLOODING, 0x009048),
drivers/net/ethernet/mscc/vsc7514_regs.c
88
REG(ANA_FLOODING_IPMC, 0x00904c),
drivers/net/ethernet/mscc/vsc7514_regs.c
89
REG(ANA_SFLOW_CFG, 0x009050),
drivers/net/ethernet/mscc/vsc7514_regs.c
90
REG(ANA_PORT_MODE, 0x009080),
drivers/net/ethernet/mscc/vsc7514_regs.c
91
REG(ANA_PGID_PGID, 0x008c00),
drivers/net/ethernet/mscc/vsc7514_regs.c
92
REG(ANA_TABLES_ANMOVED, 0x008b30),
drivers/net/ethernet/mscc/vsc7514_regs.c
93
REG(ANA_TABLES_MACHDATA, 0x008b34),
drivers/net/ethernet/mscc/vsc7514_regs.c
94
REG(ANA_TABLES_MACLDATA, 0x008b38),
drivers/net/ethernet/mscc/vsc7514_regs.c
95
REG(ANA_TABLES_MACACCESS, 0x008b3c),
drivers/net/ethernet/mscc/vsc7514_regs.c
96
REG(ANA_TABLES_MACTINDX, 0x008b40),
drivers/net/ethernet/mscc/vsc7514_regs.c
97
REG(ANA_TABLES_VLANACCESS, 0x008b44),
drivers/net/ethernet/mscc/vsc7514_regs.c
98
REG(ANA_TABLES_VLANTIDX, 0x008b48),
drivers/net/ethernet/mscc/vsc7514_regs.c
99
REG(ANA_TABLES_ISDXACCESS, 0x008b4c),
drivers/net/ethernet/sun/niu.c
150
#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
drivers/net/ethernet/sun/niu.c
152
__niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
drivers/net/ethernet/sun/niu.c
189
#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
drivers/net/ethernet/sun/niu.c
191
__niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
drivers/net/ethernet/sun/niu.c
209
#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
drivers/net/ethernet/sun/niu.c
211
__niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
drivers/net/ethernet/sun/niu.c
229
#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
drivers/net/ethernet/sun/niu.c
231
__niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
drivers/net/ipa/reg/gsi_reg-v3.1.c
13
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.1.c
16
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.1.c
176
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
178
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
180
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
182
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
184
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.1.c
187
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.1.c
190
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v3.1.c
193
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v3.1.c
196
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
198
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.1.c
201
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
drivers/net/ipa/reg/gsi_reg-v3.1.c
204
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
206
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
208
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
210
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
212
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
214
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.1.c
225
REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
13
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
16
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
187
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
189
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
191
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
193
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
195
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
198
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
201
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
204
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
207
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
209
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
212
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
215
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
217
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
219
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
221
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
223
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
225
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v3.5.1.c
236
REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
13
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.0.c
16
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.0.c
192
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
194
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
196
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
198
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
200
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.0.c
203
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.0.c
206
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.0.c
209
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.0.c
212
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
214
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.0.c
217
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.0.c
220
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
222
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
224
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
226
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
228
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
230
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.0.c
241
REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
13
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.11.c
16
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.11.c
197
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
199
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
201
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
203
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
205
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.11.c
208
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.11.c
211
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.11.c
214
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.11.c
217
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
219
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.11.c
222
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.11.c
225
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
227
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
229
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
231
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
233
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
235
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.11.c
246
REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
13
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.5.c
16
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.5.c
195
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
197
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
199
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
201
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
203
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.5.c
206
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.5.c
209
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.5.c
212
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.5.c
215
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
217
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.5.c
220
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.5.c
223
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
225
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
227
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
229
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
231
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
233
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.5.c
244
REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
13
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.9.c
16
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.9.c
196
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
198
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
200
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
202
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
204
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.9.c
207
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.9.c
210
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.9.c
213
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.9.c
216
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
218
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
drivers/net/ipa/reg/gsi_reg-v4.9.c
221
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
drivers/net/ipa/reg/gsi_reg-v4.9.c
224
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
226
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
228
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
230
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
232
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
234
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v4.9.c
245
REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
13
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v5.0.c
16
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v5.0.c
190
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00025080 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
192
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00025088 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
194
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00025090 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
196
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v5.0.c
199
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v5.0.c
202
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0002509c + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
204
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
drivers/net/ipa/reg/gsi_reg-v5.0.c
207
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
drivers/net/ipa/reg/gsi_reg-v5.0.c
210
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000250a8 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
212
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
drivers/net/ipa/reg/gsi_reg-v5.0.c
215
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
drivers/net/ipa/reg/gsi_reg-v5.0.c
218
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00025200 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
220
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00025204 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
222
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00025208 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
224
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0002520c + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
226
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00025210 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
228
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00025214 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/gsi_reg-v5.0.c
250
REG(ERROR_LOG_CLR, error_log_clr, 0x00025244 + 0x12000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v3.1.c
361
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v3.1.c
364
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v3.1.c
367
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v3.1.c
97
REG(IPA_BCR, ipa_bcr, 0x000001d0);
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
102
REG(IPA_BCR, ipa_bcr, 0x000001d0);
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
372
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
375
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
378
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.11.c
428
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.11.c
431
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.11.c
434
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.2.c
139
REG(IPA_BCR, ipa_bcr, 0x000001d0);
drivers/net/ipa/reg/ipa_reg-v4.2.c
387
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.2.c
390
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.2.c
393
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.5.c
447
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.5.c
450
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.5.c
453
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.7.c
420
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.7.c
423
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.7.c
426
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.9.c
425
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.9.c
428
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v4.9.c
431
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v5.0.c
484
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v5.0.c
487
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v5.0.c
490
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v5.5.c
483
REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v5.5.c
486
REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
drivers/net/ipa/reg/ipa_reg-v5.5.c
489
REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
181
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
183
nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
220
falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
221
level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
247
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
248
nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
278
nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
292
nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
293
nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
307
val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
319
nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
53
#define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
55
.name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
69
#define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
70
LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT)
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
78
#define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
79
LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT)
drivers/pinctrl/pinctrl-ocelot.c
1578
regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
drivers/pinctrl/pinctrl-ocelot.c
1820
err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
drivers/pinctrl/pinctrl-ocelot.c
1829
err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
drivers/pinctrl/pinctrl-ocelot.c
1902
REG(OCELOT_GPIO_OUT_SET, info,
drivers/pinctrl/pinctrl-ocelot.c
1907
REG(OCELOT_GPIO_OUT_CLR, info,
drivers/pinctrl/pinctrl-ocelot.c
1911
REG(OCELOT_GPIO_OE, info, pin),
drivers/pinctrl/pinctrl-ocelot.c
2126
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
drivers/pinctrl/pinctrl-ocelot.c
2138
REG(OCELOT_GPIO_OUT_SET, info, offset),
drivers/pinctrl/pinctrl-ocelot.c
2141
return regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
drivers/pinctrl/pinctrl-ocelot.c
2151
regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
drivers/pinctrl/pinctrl-ocelot.c
2166
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
drivers/pinctrl/pinctrl-ocelot.c
2169
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
drivers/pinctrl/pinctrl-ocelot.c
2192
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
drivers/pinctrl/pinctrl-ocelot.c
2228
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
drivers/pinctrl/pinctrl-ocelot.c
2237
regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val);
drivers/pinctrl/pinctrl-ocelot.c
2243
regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
drivers/pinctrl/pinctrl-ocelot.c
2248
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
drivers/pinctrl/pinctrl-ocelot.c
2257
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
drivers/pinctrl/pinctrl-ocelot.c
2282
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
drivers/pinctrl/pinctrl-ocelot.c
2292
regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
drivers/pinctrl/pinctrl-rockchip.c
288
#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
drivers/pinctrl/pinctrl-rockchip.c
293
.route_offset = REG, \
drivers/pinctrl/pinctrl-rockchip.c
298
#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
drivers/pinctrl/pinctrl-rockchip.c
299
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
drivers/pinctrl/pinctrl-rockchip.c
301
#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
drivers/pinctrl/pinctrl-rockchip.c
302
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
drivers/pinctrl/pinctrl-rockchip.c
304
#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
drivers/pinctrl/pinctrl-rockchip.c
305
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
drivers/ptp/ptp_clockmatrix.h
65
#define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
drivers/regulator/mc13783-regulator.c
244
MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
drivers/regulator/mc13783-regulator.c
246
MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
drivers/regulator/mc13783-regulator.c
255
MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val),
drivers/regulator/mc13783-regulator.c
256
MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val),
drivers/regulator/mc13783-regulator.c
275
MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val),
drivers/regulator/mc13783-regulator.c
286
MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val),
drivers/regulator/mc13783-regulator.c
287
MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val),
drivers/regulator/mc13783-regulator.c
288
MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val),
drivers/regulator/mc13783-regulator.c
289
MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val),
drivers/regulator/mc13783-regulator.c
290
MC13783_GPO_DEFINE(REG, PWGT1SPI, pwgt1spi, POWERMISC, mc13783_pwgtdrv_val),
drivers/regulator/mc13783-regulator.c
291
MC13783_GPO_DEFINE(REG, PWGT2SPI, pwgt2spi, POWERMISC, mc13783_pwgtdrv_val),
drivers/regulator/rn5t618-regulator.c
45
REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
46
REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
47
REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
48
REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
50
REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
51
REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
52
REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
53
REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
54
REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
56
REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1200000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
57
REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
62
REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
63
REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
64
REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
66
REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
67
REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
68
REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
69
REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
70
REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
72
REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1700000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
73
REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
78
REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
79
REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
80
REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
81
REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
82
REG(DCDC5, DC5CTL, BIT(0), DC5DAC, 0xff, 600000, 3500000, 12500),
drivers/regulator/rn5t618-regulator.c
84
REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
85
REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
86
REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
87
REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
88
REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 600000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
89
REG(LDO6, LDOEN1, BIT(5), LDO6DAC, 0x7f, 600000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
90
REG(LDO7, LDOEN1, BIT(6), LDO7DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
91
REG(LDO8, LDOEN1, BIT(7), LDO8DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
92
REG(LDO9, LDOEN2, BIT(0), LDO9DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
93
REG(LDO10, LDOEN2, BIT(1), LDO10DAC, 0x7f, 900000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
95
REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1700000, 3500000, 25000),
drivers/regulator/rn5t618-regulator.c
96
REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000),
drivers/scsi/esp_scsi.c
116
#define esp_read8(REG) esp->ops->esp_read8(esp, REG)
drivers/scsi/esp_scsi.c
117
#define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG)
drivers/scsi/mac_esp.c
49
#define esp_read8(REG) mac_esp_read8(esp, REG)
drivers/scsi/mac_esp.c
50
#define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG)
drivers/scsi/ncr53c8xx.c
1980
#define RADDR(label) (RELOC_REGISTER | REG(label))
drivers/scsi/ncr53c8xx.c
1981
#define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs)))
drivers/scsi/ncr53c8xx.h
1089
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
drivers/scsi/ncr53c8xx.h
1092
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
drivers/scsi/ncr53c8xx.h
1095
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
drivers/scsi/ncr53c8xx.h
1161
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
drivers/scsi/ncr53c8xx.h
1164
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
drivers/scsi/sun3x_esp.c
43
#define dma_read32(REG) \
drivers/scsi/sun3x_esp.c
44
readl(esp->dma_regs + (REG))
drivers/scsi/sun3x_esp.c
45
#define dma_write32(VAL, REG) \
drivers/scsi/sun3x_esp.c
46
writel((VAL), esp->dma_regs + (REG))
drivers/scsi/sun3x_esp.c
48
#define dma_read32(REG) \
drivers/scsi/sun3x_esp.c
49
*(volatile u32 *)(esp->dma_regs + (REG))
drivers/scsi/sun3x_esp.c
50
#define dma_write32(VAL, REG) \
drivers/scsi/sun3x_esp.c
51
do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
drivers/scsi/sun_esp.c
32
#define dma_read32(REG) \
drivers/scsi/sun_esp.c
33
sbus_readl(esp->dma_regs + (REG))
drivers/scsi/sun_esp.c
34
#define dma_write32(VAL, REG) \
drivers/scsi/sun_esp.c
35
sbus_writel((VAL), esp->dma_regs + (REG))
drivers/scsi/sym53c8xx_2/sym_defs.h
572
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
drivers/scsi/sym53c8xx_2/sym_defs.h
575
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
drivers/scsi/sym53c8xx_2/sym_defs.h
578
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
drivers/scsi/sym53c8xx_2/sym_defs.h
644
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
drivers/scsi/sym53c8xx_2/sym_defs.h
647
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
drivers/scsi/sym53c8xx_2/sym_fw.h
184
#define RADDR_1(label) (RELOC_REGISTER | REG(label))
drivers/scsi/sym53c8xx_2/sym_fw.h
185
#define RADDR_2(label,ofs) (RELOC_REGISTER | ((REG(label))+(ofs)))
drivers/spi/spi-realtek-rtl.c
138
value = readl(REG(RTL_SPI_SFCR));
drivers/spi/spi-realtek-rtl.c
140
writel(value, REG(RTL_SPI_SFCR));
drivers/spi/spi-realtek-rtl.c
142
value = readl(REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
147
writel(value, REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
39
value = readl(REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
44
writel(value, REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
51
value = readl(REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
57
writel(value, REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
62
while (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY))
drivers/spi/spi-realtek-rtl.c
69
writel(*buf, REG(RTL_SPI_SFDR));
drivers/spi/spi-realtek-rtl.c
76
writel(buf[0] << 24, REG(RTL_SPI_SFDR));
drivers/spi/spi-realtek-rtl.c
83
*buf = readl(REG(RTL_SPI_SFDR));
drivers/spi/spi-realtek-rtl.c
90
*buf = readl(REG(RTL_SPI_SFDR)) >> 24;
drivers/video/fbdev/controlfb.c
135
#define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
drivers/watchdog/it8712f_wdt.c
100
outb(reg, REG);
drivers/watchdog/it8712f_wdt.c
107
outb(reg++, REG);
drivers/watchdog/it8712f_wdt.c
109
outb(reg, REG);
drivers/watchdog/it8712f_wdt.c
116
outb(LDN, REG);
drivers/watchdog/it8712f_wdt.c
125
if (!request_muxed_region(REG, 2, NAME))
drivers/watchdog/it8712f_wdt.c
128
outb(0x87, REG);
drivers/watchdog/it8712f_wdt.c
129
outb(0x01, REG);
drivers/watchdog/it8712f_wdt.c
130
outb(0x55, REG);
drivers/watchdog/it8712f_wdt.c
131
outb(0x55, REG);
drivers/watchdog/it8712f_wdt.c
137
outb(0x02, REG);
drivers/watchdog/it8712f_wdt.c
139
release_region(REG, 2);
drivers/watchdog/it8712f_wdt.c
94
outb(reg, REG);
drivers/watchdog/it87_wdt.c
123
if (!request_muxed_region(REG, 2, WATCHDOG_NAME))
drivers/watchdog/it87_wdt.c
126
outb(0x87, REG);
drivers/watchdog/it87_wdt.c
127
outb(0x01, REG);
drivers/watchdog/it87_wdt.c
128
outb(0x55, REG);
drivers/watchdog/it87_wdt.c
129
outb(0x55, REG);
drivers/watchdog/it87_wdt.c
135
outb(0x02, REG);
drivers/watchdog/it87_wdt.c
137
release_region(REG, 2);
drivers/watchdog/it87_wdt.c
142
outb(LDNREG, REG);
drivers/watchdog/it87_wdt.c
148
outb(reg, REG);
drivers/watchdog/it87_wdt.c
154
outb(reg, REG);
drivers/watchdog/it87_wdt.c
162
outb(reg++, REG);
drivers/watchdog/it87_wdt.c
164
outb(reg, REG);
fs/proc/base.c
3321
REG("environ", S_IRUSR, proc_environ_operations),
fs/proc/base.c
3322
REG("auxv", S_IRUSR, proc_auxv_operations),
fs/proc/base.c
3326
REG("sched", S_IRUGO|S_IWUSR, proc_pid_sched_operations),
fs/proc/base.c
3328
REG("autogroup", S_IRUGO|S_IWUSR, proc_pid_sched_autogroup_operations),
fs/proc/base.c
3331
REG("timens_offsets", S_IRUGO|S_IWUSR, proc_timens_offsets_operations),
fs/proc/base.c
3333
REG("comm", S_IRUGO|S_IWUSR, proc_pid_set_comm_operations),
fs/proc/base.c
3337
REG("cmdline", S_IRUGO, proc_pid_cmdline_ops),
fs/proc/base.c
3340
REG("maps", S_IRUGO, proc_pid_maps_operations),
fs/proc/base.c
3342
REG("numa_maps", S_IRUGO, proc_pid_numa_maps_operations),
fs/proc/base.c
3344
REG("mem", S_IRUSR|S_IWUSR, proc_mem_operations),
fs/proc/base.c
3348
REG("mounts", S_IRUGO, proc_mounts_operations),
fs/proc/base.c
3349
REG("mountinfo", S_IRUGO, proc_mountinfo_operations),
fs/proc/base.c
3350
REG("mountstats", S_IRUSR, proc_mountstats_operations),
fs/proc/base.c
3352
REG("clear_refs", S_IWUSR, proc_clear_refs_operations),
fs/proc/base.c
3353
REG("smaps", S_IRUGO, proc_pid_smaps_operations),
fs/proc/base.c
3354
REG("smaps_rollup", S_IRUGO, proc_pid_smaps_rollup_operations),
fs/proc/base.c
3355
REG("pagemap", S_IRUSR, proc_pagemap_operations),
fs/proc/base.c
3370
REG("latency", S_IRUGO, proc_lstats_operations),
fs/proc/base.c
3382
REG("oom_adj", S_IRUGO|S_IWUSR, proc_oom_adj_operations),
fs/proc/base.c
3383
REG("oom_score_adj", S_IRUGO|S_IWUSR, proc_oom_score_adj_operations),
fs/proc/base.c
3385
REG("loginuid", S_IWUSR|S_IRUGO, proc_loginuid_operations),
fs/proc/base.c
3386
REG("sessionid", S_IRUGO, proc_sessionid_operations),
fs/proc/base.c
3389
REG("make-it-fail", S_IRUGO|S_IWUSR, proc_fault_inject_operations),
fs/proc/base.c
3390
REG("fail-nth", 0644, proc_fail_nth_operations),
fs/proc/base.c
3393
REG("coredump_filter", S_IRUGO|S_IWUSR, proc_coredump_filter_operations),
fs/proc/base.c
3399
REG("uid_map", S_IRUGO|S_IWUSR, proc_uid_map_operations),
fs/proc/base.c
3400
REG("gid_map", S_IRUGO|S_IWUSR, proc_gid_map_operations),
fs/proc/base.c
3401
REG("projid_map", S_IRUGO|S_IWUSR, proc_projid_map_operations),
fs/proc/base.c
3402
REG("setgroups", S_IRUGO|S_IWUSR, proc_setgroups_operations),
fs/proc/base.c
3405
REG("timers", S_IRUGO, proc_timers_operations),
fs/proc/base.c
3407
REG("timerslack_ns", S_IRUGO|S_IWUGO, proc_pid_set_timerslack_ns_operations),
fs/proc/base.c
3667
REG("environ", S_IRUSR, proc_environ_operations),
fs/proc/base.c
3668
REG("auxv", S_IRUSR, proc_auxv_operations),
fs/proc/base.c
3672
REG("sched", S_IRUGO|S_IWUSR, proc_pid_sched_operations),
fs/proc/base.c
3679
REG("cmdline", S_IRUGO, proc_pid_cmdline_ops),
fs/proc/base.c
3682
REG("maps", S_IRUGO, proc_pid_maps_operations),
fs/proc/base.c
3684
REG("children", S_IRUGO, proc_tid_children_operations),
fs/proc/base.c
3687
REG("numa_maps", S_IRUGO, proc_pid_numa_maps_operations),
fs/proc/base.c
3689
REG("mem", S_IRUSR|S_IWUSR, proc_mem_operations),
fs/proc/base.c
3693
REG("mounts", S_IRUGO, proc_mounts_operations),
fs/proc/base.c
3694
REG("mountinfo", S_IRUGO, proc_mountinfo_operations),
fs/proc/base.c
3696
REG("clear_refs", S_IWUSR, proc_clear_refs_operations),
fs/proc/base.c
3697
REG("smaps", S_IRUGO, proc_pid_smaps_operations),
fs/proc/base.c
3698
REG("smaps_rollup", S_IRUGO, proc_pid_smaps_rollup_operations),
fs/proc/base.c
3699
REG("pagemap", S_IRUSR, proc_pagemap_operations),
fs/proc/base.c
3714
REG("latency", S_IRUGO, proc_lstats_operations),
fs/proc/base.c
3726
REG("oom_adj", S_IRUGO|S_IWUSR, proc_oom_adj_operations),
fs/proc/base.c
3727
REG("oom_score_adj", S_IRUGO|S_IWUSR, proc_oom_score_adj_operations),
fs/proc/base.c
3729
REG("loginuid", S_IWUSR|S_IRUGO, proc_loginuid_operations),
fs/proc/base.c
3730
REG("sessionid", S_IRUGO, proc_sessionid_operations),
fs/proc/base.c
3733
REG("make-it-fail", S_IRUGO|S_IWUSR, proc_fault_inject_operations),
fs/proc/base.c
3734
REG("fail-nth", 0644, proc_fail_nth_operations),
fs/proc/base.c
3740
REG("uid_map", S_IRUGO|S_IWUSR, proc_uid_map_operations),
fs/proc/base.c
3741
REG("gid_map", S_IRUGO|S_IWUSR, proc_gid_map_operations),
fs/proc/base.c
3742
REG("projid_map", S_IRUGO|S_IWUSR, proc_projid_map_operations),
fs/proc/base.c
3743
REG("setgroups", S_IRUGO|S_IWUSR, proc_setgroups_operations),
include/linux/mfd/idtRC38xxx_reg.h
195
#define IDTFC3_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
include/soc/mscc/ocelot.h
108
#define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
sound/isa/wss/wss_lib.c
181
wss_outb(chip, CS4231P(REG), value);
sound/isa/wss/wss_lib.c
195
wss_outb(chip, CS4231P(REG), value);
sound/isa/wss/wss_lib.c
213
return wss_inb(chip, CS4231P(REG));
sound/isa/wss/wss_lib.c
221
wss_outb(chip, CS4231P(REG),
sound/isa/wss/wss_lib.c
223
wss_outb(chip, CS4231P(REG), val);
sound/isa/wss/wss_lib.c
234
wss_outb(chip, CS4231P(REG),
sound/isa/wss/wss_lib.c
237
return wss_inb(chip, CS4231P(REG));
sound/isa/wss/wss_lib.c
241
res = wss_inb(chip, CS4231P(REG));
sound/sparc/cs4231.c
301
__cs4231_writeb(chip, value, CS4231U(chip, REG));
sound/sparc/cs4231.c
334
return __cs4231_readb(chip, CS4231U(chip, REG));
tools/testing/selftests/bpf/progs/verifier_gotox.c
275
#define DEFINE_JUMP_TABLE_USE_REG(REG) \
tools/testing/selftests/bpf/progs/verifier_gotox.c
278
__naked void jump_table_use_reg_r ## REG(void) \
tools/testing/selftests/bpf/progs/verifier_gotox.c
291
r" #REG " = *(u64 *)(r0 + 0); \
tools/testing/selftests/bpf/progs/verifier_gotox.c
300
: __imm_insn(gotox_rX, BPF_RAW_INSN(BPF_JMP | BPF_JA | BPF_X, BPF_REG_ ## REG, 0, 0 , 0)) \
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
428
#define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
429
& REG##_mask)
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
430
#define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
431
& REG##_mask)
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
432
#define get32(ST, REG) (be32toh(ST.REG))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
433
#define getp32(ST, REG) (be32toh((ST)->REG))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
434
#define get64(ST, REG) (be64toh(ST.REG))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
435
#define getp64(ST, REG) (be64toh((ST)->REG))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
437
#define unget32(ST, REG) (get32(ST, REG) & ~((REG##_mask) \
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
438
<< (31-REG##_offset)))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
441
#define ungetp32(ST, REG) (getp32(ST, REG) & ~((REG##_mask) \
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
442
<< (31-REG##_offset)))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
452
#define putnn(ST, REG, X) (ST.REG = htobe32(unget32(ST, REG) | (((X) \
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
453
& REG##_mask) << (31-REG##_offset))))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
454
#define putpnn(ST, REG, X) ((ST)->REG = htobe32(ungetp32(ST, REG) \
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
455
| (((X) & REG##_mask) << (31-REG##_offset))))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
457
#define put32(ST, REG, X) (ST.REG = htobe32(X))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
458
#define putp32(ST, REG, X) ((ST)->REG = htobe32(X))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
459
#define put64(ST, REG, X) (ST.REG = htobe64(X))
tools/testing/selftests/powerpc/nx-gzip/include/nxu.h
460
#define putp64(ST, REG, X) ((ST)->REG = htobe64(X))