READ_REG
opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG);
iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
case READ_REG:
struct READ_REG read_reg;
struct READ_REG read_reg;
f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
isr = (READ_REG(priv, regISR) & IR_RUN);
READ_REG(priv, regTXF_WPTR_0);
READ_REG(priv, regRXD_WPTR_0);
master = READ_REG(priv, regINIT_SEMAPHORE);
if (!READ_REG(priv, regINIT_STATUS) && master) {
if (READ_REG(priv, regINIT_STATUS)) {
READ_REG(priv, regVPC),
READ_REG(priv, regVIC),
READ_REG(priv, regINIT_STATUS), i);
READ_REG(priv, regUNC_MAC0_A),
READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
READ_REG(priv, regUNC_MAC0_A),
READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
val = READ_REG(priv, regCLKPLL);
val = READ_REG(priv, regCLKPLL);
if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
READ_REG(priv, regRXD_CFG0_0);
if (READ_REG(priv, regRST_PORT) & 1)
READ_REG(priv, regISR);
DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
data[2] = READ_REG(priv, data[1]);
val = READ_REG(priv, reg);
val = READ_REG(priv, reg);
macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
val = READ_REG(priv, reg);
val |= ((u64) READ_REG(priv, reg + 8)) << 32;
t = READ_REG##size(astro_iop_base + addr); \
t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL;
iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
cfg_val = READ_REG(rope_cfg);
READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
(unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
(unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
(unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
(unsigned long) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
func_class = READ_REG(sba_addr + SBA_FCLASS);
fclass = READ_REG(sba_addr);
READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */