RAS_CLK_ENB
clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0,
CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0,
CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0,
CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0,