arch/powerpc/xmon/ppc-opc.c

3852

{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},

arch/powerpc/xmon/ppc-opc.c

3853

{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

3854

{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},

arch/powerpc/xmon/ppc-opc.c

3855

{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

3859

{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},

arch/powerpc/xmon/ppc-opc.c

3860

{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},

arch/powerpc/xmon/ppc-opc.c

3861

{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},

arch/powerpc/xmon/ppc-opc.c

4694

{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4695

{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4716

{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4718

{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4722

{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4723

{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4728

{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},

arch/powerpc/xmon/ppc-opc.c

4730

{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4732

{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4734

{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4756

{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4761

{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4768

{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4769

{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4774

{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4776

{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4780

{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4782

{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4784

{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},

arch/powerpc/xmon/ppc-opc.c

4796

{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},

arch/powerpc/xmon/ppc-opc.c

4800

{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4815

{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4848

{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},

arch/powerpc/xmon/ppc-opc.c

4850

{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4851

{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},

arch/powerpc/xmon/ppc-opc.c

4853

{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4855

{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4859

{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4876

{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},

arch/powerpc/xmon/ppc-opc.c

4889

{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4895

{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4897

{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4910

{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4913

{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4923

{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4924

{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4926

{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4928

{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4930

{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4941

{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4943

{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4947

{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4949

{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4955

{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4966

{"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4970

{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4979

{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4981

{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5003

{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5005

{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5007

{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5015

{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5019

{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5021

{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5051

{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5052

{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},

arch/powerpc/xmon/ppc-opc.c

5053

{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5054

{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5063

{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5068

{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5072

{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5087

{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5088

{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5102

{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5103

{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},

arch/powerpc/xmon/ppc-opc.c

5104

{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5105

{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5107

{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5114

{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5118

{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5119

{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

512

#define RAQ RA0 + 1

arch/powerpc/xmon/ppc-opc.c

5121

{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5128

{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5132

{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5134

{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5143

{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5182

{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5184

{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5189

{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5398

{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5402

{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5404

{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5412

{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5431

{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5433

{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5441

{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5442

{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5450

{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5455

{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5460

{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5464

{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5466

{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5473

{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5479

{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5481

{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5536

{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5718

{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5725

{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5727

{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5729

{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5758

{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5773

{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5777

{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5782

{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5785

{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5807

{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5811

{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5831

{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5833

{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},

arch/powerpc/xmon/ppc-opc.c

5837

{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5842

{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},

arch/powerpc/xmon/ppc-opc.c

5854

{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5857

{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5861

{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5863

{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},

arch/powerpc/xmon/ppc-opc.c

5882

{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5885

{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5901

{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5903

{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5904

{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5906

{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5907

{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5909

{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5920

{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5922

{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5928

{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5938

{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5940

{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},

arch/powerpc/xmon/ppc-opc.c

5944

{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5958

{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},

arch/powerpc/xmon/ppc-opc.c

5959

{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},

arch/powerpc/xmon/ppc-opc.c

5961

{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5963

{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5972

{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5976

{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5978

{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},

arch/powerpc/xmon/ppc-opc.c

6006

{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6007

{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6014

{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6016

{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6018

{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6019

{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6033

{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6034

{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6038

{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6040

{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6042

{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6044

{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6057

{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6058

{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6059

{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6061

{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6062

{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6068

{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6070

{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6084

{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6091

{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6092

{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6096

{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6102

{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6109

{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6111

{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6119

{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6125

{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6129

{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6134

{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6136

{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6144

{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6145

{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6149

{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6150

{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6155

{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6157

{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6159

{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6160

{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6175

{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6177

{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6179

{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6181

{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6188

{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6189

{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6197

{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6210

{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6221

{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6222

{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6231

{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6233

{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6235

{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6240

{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6242

{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6244

{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6255

{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6261

{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6263

{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6264

{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6266

{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6268

{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6283

{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6284

{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6287

{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6289

{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6293

{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6294

{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6297

{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6299

{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6303

{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6307

{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6311

{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6316

{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6318

{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6319

{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6321

{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6325

{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6329

{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6333

{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6339

{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6341

{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6342

{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6343

{"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6345

{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6347

{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6349

{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6664

{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},

arch/powerpc/xmon/ppc-opc.c

6665

{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},

arch/powerpc/xmon/ppc-opc.c

6666

{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6667

{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6668

{"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6672

{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6674

{"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

7031

{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7032

{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7033

{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7034

{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7035

{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7036

{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7037

{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7038

{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7039

{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7040

{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7041

{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7042

{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7043

{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7044

{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7045

{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7046

{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7047

{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7048

{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7049

{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},

arch/powerpc/xmon/ppc-opc.c

7051

{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

7062

{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

7063

{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

7064

{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

7076

{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

7077

{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

7078

{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

7079

{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},