R600_POWER_LEVEL_LOW
r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH);
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,
r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,
r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,
r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false);
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW);
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
pi->hw.sclks[R600_POWER_LEVEL_LOW] =
pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;
pi->hw.mclks[R600_POWER_LEVEL_LOW] =
pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
pi->hw.backbias[R600_POWER_LEVEL_LOW] =
pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] =
pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;
pi->hw.sclks[R600_POWER_LEVEL_LOW],
R600_POWER_LEVEL_LOW);
(pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40))
pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40;
sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) |
pi->hw.sclks[R600_POWER_LEVEL_LOW])) |