R600_POWER_LEVEL_HIGH
r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0);
r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH);
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,
r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
pi->hw.sclks[R600_POWER_LEVEL_HIGH] =
pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
pi->hw.mclks[R600_POWER_LEVEL_HIGH] =
pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;
pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
pi->hw.backbias[R600_POWER_LEVEL_HIGH] =
pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;
pi->hw.sclks[R600_POWER_LEVEL_HIGH],
R600_POWER_LEVEL_HIGH);
if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];
STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) |
STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));
pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
pi->hw.sclks[R600_POWER_LEVEL_HIGH])));