A64_ZR
A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX)
aarch64_insn_gen_atomic_ld_op(A64_ZR, Rn, Rs, \
#define A64_CMN_I(sf, Rn, imm12) A64_ADDS_I(sf, A64_ZR, Rn, imm12)
#define A64_CMP_I(sf, Rn, imm12) A64_SUBS_I(sf, A64_ZR, Rn, imm12)
#define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)
#define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)
#define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
#define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
A64_LOGIC_SREG(sf, Rd, A64_ZR, Rm, ORN)
#define A64_TST_I(sf, Rn, imm) A64_ANDS_I(sf, A64_ZR, Rn, imm)
emit(A64_POP(A64_ZR, ptr, A64_SP), ctx);
emit(A64_STR64I(A64_ZR, A64_SP, run_ctx_off + cookie_off), ctx);
emit(A64_STR64I(A64_ZR, A64_SP, retval_off), ctx);
emit(A64_PUSH(A64_ZR, ptr, A64_SP), ctx);
emit(A64_PUSH(reg1, A64_ZR, A64_SP), ctx);
emit(A64_POP(reg1, A64_ZR, A64_SP), ctx);