AXI_MASTER_CFG_BASE
AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
AXI_MASTER_CFG_BASE +
hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
.base_off = AXI_MASTER_CFG_BASE,
reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +