QUEUE_SIZE
CP_HQD_PQ_CONTROL, QUEUE_SIZE);
CP_HQD_PQ_CONTROL, QUEUE_SIZE);
CP_HQD_PQ_CONTROL, QUEUE_SIZE);
CP_HQD_PQ_CONTROL, QUEUE_SIZE);
CP_HQD_PQ_CONTROL, QUEUE_SIZE);
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
size_val = pio_reg_read(QUEUE_SIZE);
#define ALIGNED_QUEUE_SIZE ALIGN(QUEUE_SIZE, SZ_4K)
cq_size = QUEUE_SIZE + 1;
init_attr.max_send_wr = QUEUE_SIZE;
dmn->info.max_send_wr = QUEUE_SIZE;
SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
SCU_UFQC_GEN_VAL(QUEUE_SIZE, value)
ha->queues_len = ((REQUEST_QUEUE_DEPTH * QUEUE_SIZE) +
(RESPONSE_QUEUE_DEPTH * QUEUE_SIZE) +
(REQUEST_QUEUE_DEPTH * QUEUE_SIZE);
QUEUE_SIZE));
(REQUEST_QUEUE_DEPTH * QUEUE_SIZE) +
(RESPONSE_QUEUE_DEPTH * QUEUE_SIZE);
QUEUE_SIZE) +
QUEUE_SIZE));
if (port->write_started >= QUEUE_SIZE)
if (port->read_started >= QUEUE_SIZE)
int n = allocated ? QUEUE_SIZE - *allocated : QUEUE_SIZE;
if (address > (u32)(QUEUE_START + QUEUE_SIZE))
(u32)(QUEUE_START + QUEUE_SIZE))
struct entry entries[QUEUE_SIZE];
return QUEUE_SIZE - q->next_cons_idx + q->next_prod_idx;
int nr_free = QUEUE_SIZE - queue_len(q);
*idx = (*idx + 1) % QUEUE_SIZE;