PWR_BASEADDR_SDIO
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0) \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1) \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0) \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1) \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84}, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\