PutByte
PutByte(XIRCREG40_RXST0, (~rx_status & 0xff));
PutByte(XIRCREG40_TXST0, 0);
PutByte(XIRCREG40_TXST1, 0);
PutByte(XIRCREG_CR, ClearRxOvrun);
PutByte(XIRCREG_CR, RestartTx); /* restart transmitter process */
PutByte(XIRCREG_CR, EnableIntr); /* re-enable interrupts */
PutByte(XIRCREG_EDP, skb->data[pktlen-1]);
PutByte(XIRCREG_CR, TransmitPacket|EnableIntr);
PutByte(sa_info->reg_nr++, addr[5 - i]);
PutByte(sa_info->reg_nr++, addr[i]);
PutByte(XIRCREG42_SWC1, value | 0x06); /* set MPE and PME */
PutByte(XIRCREG42_SWC1, value | 0x02); /* set MPE */
PutByte(XIRCREG42_SWC1, value | 0x01);
PutByte(XIRCREG40_CMD0, Offline);
PutByte(XIRCREG40_CMD0, EnableRecv | Online);
PutByte(XIRCREG42_SWC1, value | 0x00);
PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */
PutByte(XIRCREG4_GPR1, 1); /* set bit 0: power up */
PutByte(XIRCREG4_GPR1, 1 | 4); /* set bit 0: power up, bit 2: AIC */
PutByte(XIRCREG_CR, SoftReset); /* set */
PutByte(XIRCREG_CR, 0); /* clear */
PutByte(XIRCREG4_GPR0, 0x0e);
PutByte(XIRCREG4_GPR0, 4);
PutByte(XIRCREG42_SWC1, 0xC0);
PutByte(XIRCREG42_SWC1, 0x80);
PutByte(XIRCREG1_IMR0, 0xff); /* allow all ints */
PutByte(XIRCREG1_IMR1, 1 ); /* and Set TxUnderrunDetect */
PutByte(XIRCREG1_ECR, value);
PutByte(XIRCREG42_SWC0, 0x20); /* disable source insertion */
PutByte(XIRCREG40_RMASK0, 0xff); /* ROK, RAB, rsv, RO, CRC, AE, PTL, MP */
PutByte(XIRCREG40_TMASK0, 0xff); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */
PutByte(XIRCREG40_TMASK1, 0xb0); /* rsv, rsv, PTD, EXT, rsv,rsv,rsv, rsv*/
PutByte(XIRCREG40_RXST0, 0x00); /* ROK, RAB, REN, RO, CRC, AE, PTL, MP */
PutByte(XIRCREG40_TXST0, 0x00); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */
PutByte(XIRCREG40_TXST1, 0x00); /* TEN, rsv, PTD, EXT, retry_counter:4 */
PutByte(XIRCREG2_MSR, GetByte(XIRCREG2_MSR) | 0x08);
PutByte(XIRCREG42_SWC1, 0xC0);
PutByte(XIRCREG42_SWC1, 0x80);
PutByte(XIRCREG1_ECR, GetByte(XIRCREG1_ECR) | FullDuplex);
PutByte(XIRCREG2_LED, 0x3b);
PutByte(XIRCREG2_LED, 0x3a);
PutByte(0x0b, 0x04); /* 100 Mbit LED */
PutByte(XIRCREG40_CMD0, EnableRecv | Online);
PutByte(XIRCREG1_IMR0, 0xff);
PutByte(XIRCREG_CR, EnableIntr);
PutByte(0x10, 0x11); /* unmask master-int bit */
PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */
PutByte(XIRCREG_CR, 0); /* disable interrupts */
PutByte(XIRCREG1_IMR0, 0x00); /* forbid all ints */
PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */
PutByte(XIRCREG2_GPR2, 0x04|0); /* drive MDCK low */
PutByte(XIRCREG2_GPR2, 0x04|1); /* and drive MDCK high */
PutByte(XIRCREG2_GPR2, 0x0c|2|0); /* set MDIO */
PutByte(XIRCREG2_GPR2, 0x0c|2|1); /* and drive MDCK high */
PutByte(XIRCREG2_GPR2, 0x0c|0|0); /* clear MDIO */
PutByte(XIRCREG2_GPR2, 0x0c|0|1); /* and drive MDCK high */
PutByte(XIRCREG2_GPR2, 4|0); /* drive MDCK low */
PutByte(XIRCREG2_GPR2, 4|1); /* drive MDCK high again */
PutByte(XIRCREG_CR, 0);