P_GCC_GPU_GPLL0_DIV_CLK_SRC
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
F(150000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 2, 0, 0),
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),