P_CMN_PLL_XO_CLK
{ P_CMN_PLL_XO_CLK, 0 },
F(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
{ P_CMN_PLL_XO_CLK, 0 },
{ P_CMN_PLL_XO_CLK, 0 },
{ P_CMN_PLL_XO_CLK, 0 },