drivers/gpu/drm/xe/xe_hwmon.c

1085

if (uval & PWR_LIM_EN) {

drivers/gpu/drm/xe/xe_hwmon.c

1122

if ((!(uval & PWR_LIM_EN)) && channel == CHANNEL_CARD) {

drivers/gpu/drm/xe/xe_hwmon.c

207

*uval = (val0 & PWR_LIM_EN) ? val0 : 0;

drivers/gpu/drm/xe/xe_hwmon.c

209

*uval = (val1 & PWR_LIM_EN) ? val1 : 0;

drivers/gpu/drm/xe/xe_hwmon.c

211

*uval = (val0 & PWR_LIM_EN) ? 1 : (val1 & PWR_LIM_EN) ? 1 : 0;

drivers/gpu/drm/xe/xe_hwmon.c

347

if (!(reg_val & PWR_LIM_EN)) {

drivers/gpu/drm/xe/xe_hwmon.c

390

xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);

drivers/gpu/drm/xe/xe_hwmon.c

393

reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);

drivers/gpu/drm/xe/xe_hwmon.c

397

if (reg_val & PWR_LIM_EN) {

drivers/gpu/drm/xe/xe_hwmon.c

437

reg_val = PWR_LIM_EN | REG_FIELD_PREP(PWR_LIM_VAL, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

706

ret = (uval & PWR_LIM_EN) ? attr->mode : 0;