drivers/gpu/drm/i915/display/intel_combo_phy.c

306

PWR_DOWN_LN_MASK, lane_mask);

drivers/gpu/drm/i915/display/intel_combo_phy_regs.h

35

#define PWR_UP_ALL_LANES REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x0)

drivers/gpu/drm/i915/display/intel_combo_phy_regs.h

36

#define PWR_DOWN_LN_3_2_1 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xe)

drivers/gpu/drm/i915/display/intel_combo_phy_regs.h

37

#define PWR_DOWN_LN_3_2 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xc)

drivers/gpu/drm/i915/display/intel_combo_phy_regs.h

38

#define PWR_DOWN_LN_3 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x8)

drivers/gpu/drm/i915/display/intel_combo_phy_regs.h

39

#define PWR_DOWN_LN_2_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x7)

drivers/gpu/drm/i915/display/intel_combo_phy_regs.h

40

#define PWR_DOWN_LN_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x3)

drivers/gpu/drm/i915/display/intel_combo_phy_regs.h

41

#define PWR_DOWN_LN_3_1 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xa)

drivers/gpu/drm/i915/display/intel_combo_phy_regs.h

42

#define PWR_DOWN_LN_3_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xb)