PWR_CMD_POLLING
case PWR_CMD_POLLING:
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1) \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1) \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0 \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0}, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
PWR_CMD_POLLING, BIT(1), 0},
PWR_CMD_POLLING, BIT(1), BIT(1)},\
PWR_CMD_POLLING, 0xFF, 0},\
PWR_CMD_POLLING, 0xFF, 0},\
PWR_CMD_POLLING, 0xFF, 0},\
PWR_CMD_POLLING, 0xFF, 0},\
PWR_CMD_POLLING, BIT(7), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
case PWR_CMD_POLLING:
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]= 0 TSF in 40M*/\
{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */ \
{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\