Symbol: PWR_CMD_WRITE
drivers/net/wireless/realtek/rtlwifi/core.c
1778
case PWR_CMD_WRITE:
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
101
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
105
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
108
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
116
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
122
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
127
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
131
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
135
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
139
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
142
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
145
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
153
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
159
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
164
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/}, \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
166
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
171
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
175
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
190
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
196
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
199
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
202
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
208
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
211
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
214
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
220
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
226
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
229
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
232
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
235
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
238
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
49
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
52
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
55
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
58
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
61
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
67
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
70
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
75
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
78
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
81
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
90
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
93
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4) \
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
97
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7) \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
100
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
111
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
117
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
125
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
128
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
131
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
135
PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
138
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
141
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
152
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
158
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
161
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
164
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
172
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
175
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
183
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
191
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
194
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
209
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
215
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
218
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
221
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
224
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
227
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
235
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
238
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
241
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
247
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
253
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
256
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
259
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
262
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
265
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
47
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
50
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
53
PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
59
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
62
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
73
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
76
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
79
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
90
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
94
PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
97
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
100
PWR_CMD_WRITE, BIT(0), BIT(0)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
112
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
118
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
127
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
131
PWR_CMD_WRITE, BIT(2), BIT(2)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
135
PWR_CMD_WRITE, BIT(0), BIT(0)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
148
PWR_CMD_WRITE, BIT(0), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
156
PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
160
PWR_CMD_WRITE, 0xFF, 0},
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
167
PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
170
PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
177
PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
185
PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
188
PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
208
PWR_CMD_WRITE, BIT(0), 0},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
214
PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
217
PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
220
PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
224
PWR_CMD_WRITE, BIT(5), BIT(5)},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
231
PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
234
PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
237
PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
244
PWR_CMD_WRITE, BIT(4), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
252
PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
256
PWR_CMD_WRITE, BIT(1), BIT(1)},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
260
PWR_CMD_WRITE, 0xFF, 0xFF},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
264
PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
267
PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
46
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
52
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
55
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
58
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
61
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
71
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
73
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
75
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
84
PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
90
PWR_CMD_WRITE, \
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
95
PWR_CMD_WRITE, BIT(3)|BIT(4), \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
102
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
105
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
108
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
116
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
120
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
123
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
126
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
132
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
136
PWR_CMD_WRITE, BIT(5), BIT(5)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
140
PWR_CMD_WRITE, BIT(0), 0},
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
148
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
152
PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
155
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
158
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
161
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
164
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
175
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
178
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
184
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
187
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
195
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
199
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
202
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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252
PWR_CMD_WRITE, 0xFF, 0x20}, \
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255
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
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113
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
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116
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
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119
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
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122
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
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125
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
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130
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
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133
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
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143
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
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146
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
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149
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
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152
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
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155
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
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164
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
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170
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
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173
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
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184
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
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190
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
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199
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
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218
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
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267
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
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452
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
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456
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
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491
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
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499
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
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520
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
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526
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
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529
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
532
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
540
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
543
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
549
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
552
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
555
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
558
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
563
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
567
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
57
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
570
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
573
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
578
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
583
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
586
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
60
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
601
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
607
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
610
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
613
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
616
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
619
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
624
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
627
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
63
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
630
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
636
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
642
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
645
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
648
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
651
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
654
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
66
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
74
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xc0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
76
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xE0}, \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
78
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
81
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
84
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
87
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
90
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
93
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
96
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
99
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
drivers/net/wireless/realtek/rtw89/mac.c
1272
case PWR_CMD_WRITE:
drivers/net/wireless/realtek/rtw89/rtw8852a.c
226
PWR_CMD_WRITE, BIT(6), BIT(6)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
231
PWR_CMD_WRITE, BIT(0), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
241
PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
246
PWR_CMD_WRITE, BIT(7), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
251
PWR_CMD_WRITE, BIT(2), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
261
PWR_CMD_WRITE, BIT(0), BIT(0)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
266
PWR_CMD_WRITE, BIT(0), BIT(0)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
276
PWR_CMD_WRITE, BIT(6), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
281
PWR_CMD_WRITE, BIT(0), BIT(0)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
286
PWR_CMD_WRITE, BIT(0), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
291
PWR_CMD_WRITE, BIT(0), BIT(0)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
296
PWR_CMD_WRITE, BIT(0), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
301
PWR_CMD_WRITE, BIT(0), BIT(0)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
306
PWR_CMD_WRITE, BIT(6), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
311
PWR_CMD_WRITE, BIT(5), BIT(5)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
316
PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
321
PWR_CMD_WRITE, BIT(1), BIT(1)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
326
PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
331
PWR_CMD_WRITE, BIT(4), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
336
PWR_CMD_WRITE, BIT(2), BIT(2)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
341
PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
354
PWR_CMD_WRITE, 0xFF, 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
359
PWR_CMD_WRITE, 0xFF, 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
364
PWR_CMD_WRITE, BIT(0), BIT(0)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
369
PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
374
PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
379
PWR_CMD_WRITE, BIT(6), BIT(6)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
384
PWR_CMD_WRITE, BIT(1), BIT(1)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
394
PWR_CMD_WRITE, BIT(0), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
399
PWR_CMD_WRITE, BIT(4), BIT(4)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
404
PWR_CMD_WRITE, BIT(2), BIT(2)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
409
PWR_CMD_WRITE, BIT(4), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
414
PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
419
PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
425
PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
drivers/net/wireless/realtek/rtw89/rtw8852a.c
430
PWR_CMD_WRITE, BIT(0), BIT(0)},
drivers/staging/rtl8723bs/hal/HalPwrSeqCmd.c
65
case PWR_CMD_WRITE:
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
101
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
102
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
103
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
104
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
105
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
106
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
112
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
113
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
115
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
116
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
117
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
118
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
124
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
125
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
126
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
127
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
132
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
133
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
138
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
140
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
141
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
142
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
143
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
144
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
150
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
151
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
152
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
154
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
156
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
157
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
158
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
159
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
160
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
166
{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
167
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
168
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
169
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
170
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
171
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
172
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
173
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
174
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
175
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
176
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
177
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
178
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
179
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
182
{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
183
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
184
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
185
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
186
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
193
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
194
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
195
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
196
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
197
{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
198
{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
199
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
200
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
201
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
202
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
203
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
206
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
207
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
42
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
43
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
45
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital , 1:isolation*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
46
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
47
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB suspend */ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
49
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* Enable USB suspend */ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
50
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
51
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]= 0*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
52
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
53
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
55
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
56
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
57
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
58
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
59
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
60
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
61
{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
62
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
68
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
69
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
70
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
71
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
73
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
74
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital , 1:isolation*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
75
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
81
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
82
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
83
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
84
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
85
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
86
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
92
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
93
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
95
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
drivers/staging/rtl8723bs/include/hal_pwr_seq.h
96
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/