PWR_CTL_EN
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
"reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
PWR_CTL_EN, value, 4);
status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
PWR_CTL_EN, value, 4);
cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
cx231xx_coredbg("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN,
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
PWR_CTL_EN, value, 4);
status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
cx231xx_coredbg("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN,