arch/loongarch/kernel/asm-offsets.c

205

DEFINE(_PTE_T_LOG2, PTE_T_LOG2);

arch/mips/include/asm/pgtable-32.h

65

# define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2 - 1)

arch/mips/include/asm/pgtable-32.h

67

# define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2)

arch/mips/include/asm/pgtable-32.h

78

# define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)

arch/mips/include/asm/pgtable-32.h

80

# define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)

arch/mips/kernel/asm-offsets.c

212

DEFINE(_PTE_T_LOG2, PTE_T_LOG2);

arch/mips/mm/tlbex.c

2015

UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT - PTE_T_LOG2);

arch/mips/mm/tlbex.c

2016

uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);

arch/mips/mm/tlbex.c

2451

pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)

arch/mips/mm/tlbex.c

957

unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;

arch/mips/mm/tlbex.c

958

unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);

arch/powerpc/include/asm/nohash/32/mmu-44x.h

153

#define PPC44x_PTE_ADD_SHIFT (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)

arch/powerpc/include/asm/nohash/32/mmu-44x.h

154

#define PPC44x_PTE_ADD_MASK_BIT (32 - PTE_T_LOG2 - PTE_SHIFT)

arch/powerpc/include/asm/page_32.h

17

#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */

arch/powerpc/include/asm/page_32.h

19

#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */

arch/powerpc/kernel/asm-offsets.c

636

DEFINE(PTE_T_LOG2, PTE_T_LOG2);