PSR_I_BIT
msr cpsr_c, #PSR_I_BIT | SVC_MODE
tst \oldcpsr, #PSR_I_BIT
orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
(PSR_J_BIT | PSR_E_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | \
#define IRQMASK_I_BIT PSR_I_BIT
(!((regs)->ARM_cpsr & PSR_I_BIT))
if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE),
PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
regs->ARM_cpsr |= PSR_I_BIT;
regs->ARM_cpsr &= ~PSR_I_BIT;
write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \
#define DAIF_PROCCTX_NOIRQ (PSR_I_BIT | PSR_F_BIT)
#define DAIF_ERRCTX (PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
#define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
flags |= PSR_I_BIT | PSR_F_BIT;
bool irq_disabled = flags & PSR_I_BIT;
(read_sysreg(daif) & (PSR_I_BIT | PSR_F_BIT)) != (PSR_I_BIT | PSR_F_BIT));
flags &= ~(PSR_I_BIT | PSR_F_BIT);
#define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
return flags & PSR_I_BIT;
(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
return (regs->pstate & PSR_I_BIT) || !irqs_priority_unmasked(regs);
(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h)
pstate & PSR_I_BIT ? 'I' : 'i',
(regs->pstate & PSR_I_BIT) == 0 &&
WARN_ON(!(cpuflags & PSR_I_BIT));
spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT |
new |= PSR_I_BIT;
new_spsr |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT;
#define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \
#define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \
uc->uc_mcontext.pstate |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT;