PSR_F_BIT
orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
(PSR_J_BIT | PSR_E_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | \
(!((regs)->ARM_cpsr & PSR_F_BIT))
regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE),
PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
#define PSR_IGNORE_BITS (PSR_A_BIT | PSR_F_BIT)
write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \
#define DAIF_PROCCTX_NOIRQ (PSR_I_BIT | PSR_F_BIT)
#define DAIF_ERRCTX (PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
#define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
flags |= PSR_I_BIT | PSR_F_BIT;
(read_sysreg(daif) & (PSR_I_BIT | PSR_F_BIT)) != (PSR_I_BIT | PSR_F_BIT));
flags &= ~(PSR_I_BIT | PSR_F_BIT);
#define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h)
pstate & PSR_F_BIT ? 'F' : 'f',
(regs->pstate & PSR_F_BIT) == 0) {
WARN_ON(!(cpuflags & PSR_F_BIT));
spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT |
new |= PSR_F_BIT;
new_spsr |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT;
PSR_F_BIT | PSR_D_BIT)
PSR_F_BIT | PSR_D_BIT)
uc->uc_mcontext.pstate |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT;