Symbol: PP_STATUS
drivers/gpu/drm/gma500/cdv_intel_dp.c
429
if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {
drivers/gpu/drm/gma500/cdv_intel_dp.c
430
DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS));
drivers/gpu/drm/gma500/cdv_intel_dp.c
461
DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS));
drivers/gpu/drm/gma500/cdv_intel_dp.c
463
if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {
drivers/gpu/drm/gma500/cdv_intel_lvds.c
121
pp_status = REG_READ(PP_STATUS);
drivers/gpu/drm/gma500/cdv_intel_lvds.c
132
pp_status = REG_READ(PP_STATUS);
drivers/gpu/drm/gma500/oaktrail_device.c
207
pp_stat = PSB_RVDC32(PP_STATUS);
drivers/gpu/drm/gma500/oaktrail_device.c
317
pp_stat = PSB_RVDC32(PP_STATUS);
drivers/gpu/drm/gma500/oaktrail_device.c
322
pp_stat = PSB_RVDC32(PP_STATUS);
drivers/gpu/drm/gma500/oaktrail_lvds.c
50
pp_status = REG_READ(PP_STATUS);
drivers/gpu/drm/gma500/oaktrail_lvds.c
61
pp_status = REG_READ(PP_STATUS);
drivers/gpu/drm/gma500/psb_intel_lvds.c
224
pp_status = REG_READ(PP_STATUS);
drivers/gpu/drm/gma500/psb_intel_lvds.c
235
pp_status = REG_READ(PP_STATUS);
drivers/gpu/drm/gma500/psb_intel_lvds.c
323
pp_status = REG_READ(PP_STATUS);
drivers/gpu/drm/gma500/psb_intel_lvds.c
329
pp_status = REG_READ(PP_STATUS);
drivers/gpu/drm/i915/display/intel_display_power.c
1223
intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,
drivers/gpu/drm/i915/display/intel_lvds.c
332
if (intel_de_wait_for_set_ms(display, PP_STATUS(display, 0), PP_ON, 5000))
drivers/gpu/drm/i915/display/intel_lvds.c
348
if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_ON, 1000))
drivers/gpu/drm/i915/display/intel_lvds.c
387
if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_CYCLE_DELAY_ACTIVE, 5000))
drivers/gpu/drm/i915/display/intel_pps.c
282
return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;
drivers/gpu/drm/i915/display/intel_pps.c
514
regs->pp_stat = PP_STATUS(display, pps_idx);