PSB_RSGX32
val = PSB_RSGX32(PSB_CR_BIF_CTRL);
(void)PSB_RSGX32(PSB_CR_BIF_CTRL);
driver->bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL);
(void)PSB_RSGX32(PSB_CR_BIF_CTRL);
u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
PSB_RSGX32(PSB_CR_CLKGATECTL);
PSB_RSGX32(PSB_CR_SOFT_RESET);
PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_CB_CTRL_CLEAR_FAULT,
(void) PSB_RSGX32(PSB_CR_BIF_CTRL);
PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_CB_CTRL_CLEAR_FAULT,
(void) PSB_RSGX32(PSB_CR_BIF_CTRL);
PSB_RSGX32(PSB_CR_BIF_BANK1);
PSB_WSGX32((PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_MMU_ER_MASK),
PSB_RSGX32(PSB_CR_BIF_CTRL);
PSB_RSGX32(PSB_CR_BIF_TWOD_REQ_BASE); /* Post */
val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */