drivers/gpu/drm/gma500/cdv_device.c

254

regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_device.c

337

REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2018

pp_on = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2022

REG_WRITE(PP_CONTROL, pp_on);

drivers/gpu/drm/gma500/cdv_intel_dp.c

389

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

392

REG_WRITE(PP_CONTROL, pp);

drivers/gpu/drm/gma500/cdv_intel_dp.c

393

REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

403

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

406

REG_WRITE(PP_CONTROL, pp);

drivers/gpu/drm/gma500/cdv_intel_dp.c

407

REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

422

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

426

REG_WRITE(PP_CONTROL, pp);

drivers/gpu/drm/gma500/cdv_intel_dp.c

427

REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

447

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

459

REG_WRITE(PP_CONTROL, pp);

drivers/gpu/drm/gma500/cdv_intel_dp.c

460

REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

484

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

487

REG_WRITE(PP_CONTROL, pp);

drivers/gpu/drm/gma500/cdv_intel_dp.c

500

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

503

REG_WRITE(PP_CONTROL, pp);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

118

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |

drivers/gpu/drm/gma500/cdv_intel_lvds.c

129

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &

drivers/gpu/drm/gma500/oaktrail_device.c

175

regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);

drivers/gpu/drm/gma500/oaktrail_device.c

204

PSB_WVDC32(0, PP_CONTROL);

drivers/gpu/drm/gma500/oaktrail_device.c

312

PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);

drivers/gpu/drm/gma500/oaktrail_lvds.c

47

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |

drivers/gpu/drm/gma500/oaktrail_lvds.c

58

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &

drivers/gpu/drm/gma500/psb_intel_lvds.c

221

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |

drivers/gpu/drm/gma500/psb_intel_lvds.c

232

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &

drivers/gpu/drm/gma500/psb_intel_lvds.c

265

lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

316

REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

320

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |

drivers/gpu/drm/gma500/psb_intel_lvds.c

326

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

364

intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON,

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

371

intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE,

drivers/gpu/drm/i915/display/intel_lvds.c

163

PP_CONTROL(display, 0)) & PANEL_POWER_RESET;

drivers/gpu/drm/i915/display/intel_lvds.c

216

val = intel_de_read(display, PP_CONTROL(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

221

intel_de_write(display, PP_CONTROL(display, 0), val);

drivers/gpu/drm/i915/display/intel_lvds.c

329

intel_de_rmw(display, PP_CONTROL(display, 0), 0, PANEL_POWER_ON);

drivers/gpu/drm/i915/display/intel_lvds.c

347

intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, 0);

drivers/gpu/drm/i915/display/intel_pps.c

1768

intel_de_rmw(display, PP_CONTROL(display, pps_idx),

drivers/gpu/drm/i915/display/intel_pps.c

1828

pp_reg = PP_CONTROL(display, 0);

drivers/gpu/drm/i915/display/intel_pps.c

1851

pp_reg = PP_CONTROL(display, pipe);

drivers/gpu/drm/i915/display/intel_pps.c

1856

pp_reg = PP_CONTROL(display, 0);

drivers/gpu/drm/i915/display/intel_pps.c

287

return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;

drivers/gpu/drm/i915/display/intel_pps.c

513

regs->pp_ctrl = PP_CONTROL(display, pps_idx);