PRG_ETH0
clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;
clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_EXT_PHY_MODE_MASK,
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK |
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,