arch/powerpc/xmon/ppc-opc.c

3036

{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},

arch/powerpc/xmon/ppc-opc.c

5052

{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},

arch/powerpc/xmon/ppc-opc.c

5054

{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5093

{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},

arch/powerpc/xmon/ppc-opc.c

5103

{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},

arch/powerpc/xmon/ppc-opc.c

5105

{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5219

{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},

arch/powerpc/xmon/ppc-opc.c

5243

{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},

arch/powerpc/xmon/ppc-opc.c

5244

{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},

arch/powerpc/xmon/ppc-opc.c

5245

{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},

arch/powerpc/xmon/ppc-opc.c

5416

{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},

arch/powerpc/xmon/ppc-opc.c

5417

{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},

arch/powerpc/xmon/ppc-opc.c

5418

{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},

arch/powerpc/xmon/ppc-opc.c

5583

{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5844

{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},

arch/powerpc/xmon/ppc-opc.c

6268

{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6337

{"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},

arch/powerpc/xmon/ppc-opc.c

6674

{"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},