PORT_PLL_P2_MASK
#define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0);
hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);
p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));