Symbol: PORT_PLL_P1_MASK
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
48
#define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2091
PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0);
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2212
hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
2399
clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);
drivers/gpu/drm/i915/gvt/handlers.c
599
p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));