PP_SMC_POWER_PROFILE_COUNT
extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
uint32_t workload_refcount[PP_SMC_POWER_PROFILE_COUNT];
static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
PP_SMC_POWER_PROFILE_COUNT);
static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
static struct cmn2asic_mapping smu_v14_0_2_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
for (profile_mode = 0; profile_mode < PP_SMC_POWER_PROFILE_COUNT; profile_mode++) {
if (index >= PP_SMC_POWER_PROFILE_COUNT ||