PP_SCLK
ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);
ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);
if (type != PP_SCLK)
return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
case PP_SCLK:
case PP_SCLK:
smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
case PP_SCLK:
case PP_SCLK:
smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
case PP_SCLK:
case PP_SCLK:
case PP_SCLK:
vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
case PP_SCLK:
vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
case PP_SCLK:
case PP_SCLK:
case PP_SCLK:
vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
case PP_SCLK:
case PP_SCLK:
case PP_SCLK: