PPCLK_UCLK
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
if (clk == PPCLK_UCLK)
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
case PPCLK_UCLK:
if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
dcn401_init_single_clock(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
case PPCLK_UCLK:
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);
success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);
(PPCLK_UCLK << 16) | (min_freq & 0xffff),
(PPCLK_UCLK << 16) | (min_freq & 0xffff),
(PPCLK_UCLK << 16) | (max_freq & 0xffff),
vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16),
(PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
PPCLK_UCLK)) == 0,
(PPCLK_UCLK << 16) | (min_freq & 0xffff),
(PPCLK_UCLK << 16) | (max_freq & 0xffff),
ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
PPCLK_UCLK,
(PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
(PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete)
*value = metrics->CurrClock[PPCLK_UCLK];
case PPCLK_UCLK:
(PPCLK_UCLK << 16) | (freq & 0xffff),
if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete)
case PPCLK_UCLK:
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
*value = metrics->CurrClock[PPCLK_UCLK];
*value = metrics->CurrClock[PPCLK_UCLK];
*value = metrics->CurrClock[PPCLK_UCLK];
*value = metrics->CurrClock[PPCLK_UCLK];
if (!table_member[PPCLK_UCLK].SnapToDiscrete)
case PPCLK_UCLK:
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
*value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
metrics->CurrClock[PPCLK_UCLK];
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
*value = metrics->CurrClock[PPCLK_UCLK];
case PPCLK_UCLK:
(PPCLK_UCLK << 16) | (freq & 0xffff),
case PPCLK_UCLK:
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
*value = metrics->CurrClock[PPCLK_UCLK];
(PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
case PPCLK_UCLK:
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
*value = metrics->CurrClock[PPCLK_UCLK];
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
*value = metrics->CurrClock[PPCLK_UCLK];
case PPCLK_UCLK: